Abstract: In exemplary embodiments, methods and apparatuses for securing electronic devices against tampering or unauthorized modifications are presented herein. One or more system locks may be installed in the system at a location between two or more subsystems along a communications path. Each system lock may be associated with a particular subsystem. The system locks may monitor the state of the system, including transactions targeting associated subsystems, and the transactions and/or state of the system may be compared to known valid transactions and states. If the requested transaction or enacted system state differs from a known acceptable transaction or state, a notification may be generated and countermeasures may be enacted. In some embodiments, the system locks may be located in a system bus on an electronic device to ensure that software executed on the electronic device remains free of tampering.

Abstract: Exemplary embodiments provide methods and systems of authenticating an integrated circuit (IC). The manufacturing location of an IC is authenticated by storing in the IC a local signature derived from a GPS signal that was received at the manufacturing location at the time of manufacture. A remote signature is derived from a GPS signal that was received at a remote site nearly simultaneously as the reception of the GPS signal at the manufacturing location. The local signature is compared to the remote signature at an authentication site to determine the authenticity of the IC.

Abstract: A method and system for verifying an integrated circuit using a Model Checker at post-silicon time to improve post-silicon assertion-based verification. A dialog is established between the Model Checker and a fabricated integrated circuit under test (ICUT), to increase the state space which is explored. ICUT-based traces from the integrated current are generated, in part based on initial states and assertions provided by the Model Checker or by a user. The Model Checker verifies the integrated circuit by generating Model Checker-based traces from basic logic, which are reproductions of the ICUT-based traces.

Abstract: A method that enables testing any point (target point) within a core, including a point within a combinatorial circuit of a core, permits testing of points that are not otherwise unobservable in normal debugging processes. Such a target point is tested by identifying a fanout cone from that point to observable outputs, and by performing one or more tests, where each test sensitizes one or more paths that extend the signal of the target point, or its complement, to one or more of the observable outputs, and ascertains the values at those observable outputs. By having more than one observable output at which the signal of target point (or its complement) is tested significantly increases the level of confidence in the test when the observable points concur in the signal value of the target point.

Abstract: Assertion checking is achieved by modifying a given set of assertions to include subsuming assertions that cover one or more of given assertions and also require less logic to implement, by implementing at least the subsuming assertions in functionally reconfigurable circuitry within an integrated circuit, and by checking with an auxiliary tester assertions that each of the firing subsuming assertion replaced.

Abstract: A method and system is provided for Network-on-Chip (NoC) and other integrated circuit architectures. A configurable fabric circuit (CFC) is interfaced with one or more core circuits and the CFC is responsive to an input signal and capable of reconfiguring the logic circuit in the CFC in accordance with an operational mode determined based on the received input signal to facilitate a core circuit interfaced therewith to carry out an operation consistent with the operational mode.

Abstract: Serial assertion checking is realized in a System On a Chip (SoC) device by connecting scan chain output to a bit extractor configured within a functionally reconfigurable module that is part of the SoC, which extracts the bits necessary for the assertion checking. The extracted bits are applied to a finite state machine that implements the assertion checking.

Abstract: When, in the course of an integrated circuit's functional test an assertion fires at clock k, the operational clock is stopped, the sequence is reapplied to capture inputs to the assertion circuit that fired, signals within the assertion circuit are computed, and the error is backtraced. Once one or more inputs of the assertion circuit are identified as potentially the source of the error, the process of backtracing is performed for each such input. When the input that is potentially the source of the error emanates from a memory circuit, the fanin cone of the memory circuit is identified and the process of backtracing through the last-identified fanin cone is undertaken for clock k?1. This is repeated iteratively until either a module of the integrated circuit is found to be the source of the error, or the error is extended to inputs of the SoC.

Abstract: An arrangement that includes a core with a flaw is effectively made error free with an auxiliary circuit that interacts with input and output leads of the core, which detected occurrence of an input that causes an erroneous output at the core, and modified that output either essentially directly, or through changes in accessible core inputs.

Abstract: An SoCs with functionally reconfigurable modules employing the modules to configure circuitry for performing assertion checking. Both at-speed assertion checking as well as continuous single step (CSS) assertion checking is disclosed. Advantageously, the checking of the various cores within the SoC is carried out concurrently, in subsets of the entire set of assertions that need to be checked out. Advantageously, bit extraction and injection is used in CSS assertion checking to permit use of relatively small registers for the assertion checking of each subset of assertions.

Abstract: An exceptionally effective SoC design is achieved by the user of wrappers that comprise a functionally reconfigurable module (FRM) that is capable of affecting the operational functionality of the wrapper and that, consequently, is capable of affecting the operational functionality of a designed SoC. One embodiment of a core+wrapper combination comprises distinct input and output cells within the wrapper, and a separate FRM. Another embodiment may embed the input and output cells within the FRM. The FRM may be implemented with, for example, a field programmable logic array (FPLA). An additional advance is realized by providing a number of spare leads in the signal paths network that interconnects the various SoC elements.