Abstract: A Pulse Clock Delay (PCD) apparatus (208) includes a selectable plurality (Nd) of series-connected pulse transition delay units (209) from a total plurality (Nmax) of such units. Each unit provides an incremental transition delay interval DELTA t. The PCD may be connected to a first intermediate proximal node (n1a) and an adjacent electrically isolated second intermediate node (n1b) where the first and second intermediate nodes are in a shorter (215a, 215b) of two signal paths having respective proximal and spaced apart distal ends (212, 216) in an electrical network.