Abstract: A CMOS integrated circuit, in which the PMOS devices each include a buried channel region (26). The P+ source/drain regions (54) and (56) are separated from the channel region (26) by N-type lateral field isolating regions (58) and (60). Whenever a voltage negative enough to turn on the channel is applied, the isolating regions will be inverted by the electric fields from the comers of the gate. Thus, the value of the transistor's threshold voltage is not changed. However, these lateral field isolating regions provide an electric field modification which helps to minimize drain-induced barrier lowering, and thereby reduces the leakage current of the device in the off state. Preferably the lateral field isolating regions are formed by a doping which is maximal at the same depth (below the gate oxide) at which the threshold-voltage-adjust doping of the channel is maximal. The preferred CMOS process provides lateral field isolating regions on the PMOS devices, and also provides LDD regions on the NMOS devices.

Abstract: A ones bit density monitor is disclosed which is comprised of a 31-bit shift register, a counter, and a clock circuit having logic to preclude the number representing a number of pulses within the shift register from changing whenever a pulse is simultaneously input and output from the 31-bit shift register. To accomplish this, the counter increments every time a pulse is input to the 31-bit shift register and is decremented every time a pulse is output from the 31-bit shift register. Once the count reaches the number four, the ones density monitor circuit, and more specifically the counter, outputs a signal reflecting that a carrier is back on line.

Abstract: A circuit positioned in a substantially token-shaped body, the circuit that comprises (a) a serial port to receive and transmit information following a write signal, a read signal, and a program signal; (b) a scratchpad memory coupled to the serial port to hold information that is received or transmitted; (c) an electrically programmable memory coupled to the scratchpad memory; (d) program port to receive program information and program the electrically programmable memory, said program port deriving all voltages necessary to program said electrically programmable memory from said program signal; and (e) control logic coupled to the serial port and the scratchpad memory and the electrically programmable memory, the control logic transfers information to and from the scratchpad memory to the electrically programmable memory as a block pursuant to a block transfer command received at the serial port.

Abstract: A real time clock plus user memory and extra memory integrated in a single circuit with access to the extra memory either by direct addressing or by providing the address as data to specified addresses in the user memory. Further, the user memory has two banks with the same addresses, and bank selection derives from a bit in another portion of the user memory.

Abstract: A power regulator for providing a fixed output voltage that is consistent with a reference voltage and independent of a varying power supply, includes a first input connected to a reference voltage generator; a second input adapted to be connected to a varying power supply; two outputs for connection to circuitry such as oscillators; a charge pump; and three transistors. The drain and gate of the first transistor are connected to the charge pump and the source is connected to the reference voltage generator; the gate of the first transistor is coupled to the gates of the second and third transistors; and the sources of the second and third transistors are coupled one of the two outputs.

Abstract: Digital signal delay lines with electrically programmable and trimmable delay times, including electrically erasable and reprogrammable delay times. Floating gate field effect transistors are programmed to select current, capacitance, and/or threshold and thereby set a delay time determined by acurrent charging of a capacitor up to a threshold voltage. Trimming after packaging avoids package offsets. Temperature and power supply voltage compensation by current combining gives compensation compatible with the electrical programming.

Abstract: A socket system that comprises a printed circuit board; an electrical module; and a socket having a hollow core. The socket holds the electrical module and is capable of electrically coupling the electrical module to the printed circuit board. The electrical module has at least one electrical lead. The socket has at least one electrical lead capable of electrically coupling with the electrical lead(s) of the electrical module. The electrical module comprises a second printed circuit board having a first and second surface; a lithium battery positioned on the first surface of the second printed circuit board and electrically coupled with the second printed circuit board, a crystal positioned on the first surface of said second printed circuit board and electrically coupled with the second printed circuit board, and an integrated circuit positioned on the second surface of the second printed circuit board.

Abstract: An amplifier for providing a pole/zero compensated output signal by generating multiple pole/zero pairs at predetermined increasing frequencies, with the number of pole/zero pairs occurring at the increasing frequencies increasing geometrically. The amplifier includes three amplifier circuits cascaded in series to generate a first pole/zero pair at a predetermined frequency, and a second and a third pole/zero pair both generated at a second frequency two octaves above the first pole/zero pair. The first amplifier circuit configured to generate the first pole/zero pair and the second and third amplifier circuits each configured to generate the second and third pole/zero pairs. The relative spacing between each pole and its corresponding zero determines the amount of compensation performed.

Abstract: A temperature detector comprises temperature sensing circuitry calibration circuitry, and power regular circuitry. The temperature sensing circuitry has an output that varies with a temperature to create a temperature variation. The calibration circuitry is coupled to receive the output that varies with temperature to create a temperature variation. The calibration circuitry interprets the temperature variation and outputs a value that represents the temperature. The power supply regulator circuitry coordinates power to the temperature sensing circuitry. Alternate embodiments of the temperature detector comprise temperature sensing circuitry, calibration circuitry, and resolution enhancement circuitry. The temperature sensing circuitry has an output that varies with a temperature to create a temperature variation. The calibration circuitry is coupled to receive the output that varies with temperature to create a temperature variation.

Abstract: The present invention overcomes the aforementioned shortcomings and deficiencies of the prior art by providing a circuit for processing an AC signal having a peak to peak envelope associated therewith, this circuit including structure for detecting the upper edge of the peak to peak envelope of the AC signal, structure for detecting the lower edge of the peak to peak envelope of the AC signal, structure for sampling the AC signal at a mid range upper point, and structure for sampling the AC signal at a mid range lower point.

Abstract: A low power timekeeping system utilizes a state machine to first read seconds stored in a RAM and update seconds and then determine if the minutes requires updating. If the minutes do not require updating then the sequencer stops operation until the next update cycle. Similarly, the minutes, hours, days of the week, date of the month, month, and year are updated only as needed in each update cycle thereby lowering the power requirement needed by the timekeeping system.

Abstract: A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude. An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module's battery. A protocol has been specified so that the module never sources current to the data line of the one-wire bus, but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge of a voltage signal from the host. The time delay circuit in the module defines a delay, after which (in write mode) the module test the data state of the data line. In read mode, after a falling edge of a voltage signal from the host the module does or does not turn on a pull-down transistor, depending on the value of the bit read.

Abstract: A serial-port memory is positioned in a substantially token-shaped body. The substantially token-shaped body has a perimeter and a flange extending from a portion of the perimeter. The serial-port memory comprises a serial port, a scratchpad memory coupled to the serial port, a second memory coupled to the scratchpad memory; and control logic coupled to the serial port and the scratchpad and second memories. The control logic transfers information from the scratchpad memory to the second memory as a block pursuant to a block transfer command received at the serial port.

Abstract: A secure monetary system comprises an electronic module and equipment to access the electronic module. The electronic module comprising a substantially token-shaped module and secure memory circuitry to store monetary information. The secure memory positioned in the substantially token-shaped module. The equipment accesses and manipulates the monetary information stored in the memory in the electronic module. The equipment comprises memory to store control and encryption programs and the memory is coupled to a microprocessor, which is also coupled to the electronic module and a control panel. The microprocessor is secure.

Abstract: A low-power secure memory in which block move operations are performed without extensive write operations. A translation register holds a set of pointers which affect the address decoding. By changing the values in this special register, the logical addresses of the physical SRAM cell locations in the memory array (or arrays) to be changed without performing any write operations in the array. This avoids the charge consumption which would otherwise be required for charging and discharging bitlines as the memory cells are read and written to.The chip of the preferred embodiment includes a scratchpad memory as well as multiple secure memories (multiple "subkeys"). The Move Block command can transfer a block of data from the Scratch Pad directly into the corresponding block location within a secure subkey, or can replace the entire contents of a secure subkey partition (including the ID and Password fields) with the entire contents of the Scratch Pad.