Abstract: A method for joining a plurality of reticles is used for producing a semiconductor layout pattern, so that the reticles will collectively map a circuit arrangement on a semiconductor substrate. A plurality of matching patterns is provided that are each geometrically linked to a respective particular reticle and through detecting pairwise correspondence among the matching patterns likewise correspondence among the associated reticles is ascertained. In particular, the method has bulk sub-reticles and peripheral sub-reticles, and a first matching pattern associates to a peripheral sub-reticle that abuts a bulk sub-reticle and a second matching pattern to the bulk sub-reticle at such distance therefrom that fitting of the peripheral sub-reticle between the second matching pattern and the bulk sub-reticle allows matching of the first and second matching patterns. The bulk sub-reticles are used to constitute an array of sub-reticles.

Abstract: A CMOS imaging facility is implemented on a substrate through a set of pixel circuits that are array-wise organized in lines and columns and each comprise a radiation-to-charge accumulator (20), a transfer transistor (22) for transferring a representation of the charge, a reset transistor (24) fed by a reference voltage and a source follower transistor (26) for feeding a select transistor (28) that feeds the representation to an output array conductor. In particular, for respective pairs of adjacent column conductors the associated pixel transfer transistors will controllably pair wise share the accumulators in an interlace organization.

Abstract: The invention relates to a semiconductor device with a semiconductor body comprising a CMOS image sensor with an active region having viewed in projection first sides and second sides perpendicular to the first sides said active region comprising a matrix of active pixels arranged in rows and columns, each pixel having a photosensitive region, the device further comprising a plurality of circuit elements for operating the pixel in the image forming process, the plurality of circuit elements comprising a first set of circuit elements for read-out of the columns and a second set of circuit elements for controlling the rows. According to the invention a first part of the plurality of circuit elements is positioned outside the matrix along one of the first sides and a second part of the plurality of circuit elements is positioned within the matrix of active pixels remote from the second sides.

Abstract: An array-based C-MOS sensor device is provided with a facility for on the basis of non-destructive cell readout generating a radiation dose-sensing signal. In particular, the facility is arranged for accessing a subset of multiple distributed C-MOS cells across the array and feeding by such accessed cells an algorithmic means for therein generating an overall feedback dose control signalization and/or an over-all trigger signalization.

Abstract: A CMOS-based sensor apparatus comprises an array of sensor cells that are interconnected by a first set of vertical driver lines to a selective driver facility and by a second set of horizontal sensing lines to a sensing facility for sensing respectively sensed amounts of radiation. In particular, the sensor cells through being appropriately spaced in at least either row or column direction, comprise a redundancy facility that is selectively activatable for isolating an interconnect short on the basis of externally applied control actuation.

Abstract: A method for in a multi-pixel pick-up element reducing a pixel-based resolution and/or effecting anti-aliasing through selectively combining selective primary pixel outputs to combined secondary pixel outputs, comprises the following steps: row-wise, whether or not restrictively, selecting pixels for loading into a first parallel-in register; serial shifting of the load within the register for aligning selected first pixels in the first parallel-in register with selected second pixels not in the first parallel-in register; arithmetically combining pixel groups so aligned; and outputting combination results from preselected multi-pixel configurations as secondary pixels. The invention is applicable to a selection from amongst a two-dimensional pick-up array, an Interline Architecture, a Frame Transfer Architecture, a combination of those two, a TDI pick-up array, and a linear pick-up array, and for both mono-color and multi-color pick-up facilities.

Abstract: A charge multiplication amplifier device comprises a series arrangement of a first separation barrier facility, a temporary storage well for charge carriers, a second charge transfer barrier facility, an impact ionization facility that is operative through electric field strength effective on mobile charge carriers, and a charge collection well for receiving charge carriers so multiplied. Advantageously, the device comprises a charge collection and transfer facility (32) that is geometrically disposed next to the impact ionization facility (31) whereas impact ionization facility is controlled at a substantially static electric potential (DC1, DC2) for controlling the electric field strength. Advantageously, another embodiment of this device comprises charge collection and transfer facilities (41, 42) implemented as two (or more) independently clocked signals ?1, ?2 that require nearly two times less swing to achieve same effect.

Abstract: A method of adaptive pixel correction of a multi-color matrix from a sensor includes collecting pixel values, generating plural vectors, normalizing values and determining an estimated value. The collecting pixel values collects values of a two-dimensional multi-pixel kernel around a particular pixel from the multi-color matrix. The generating plural vectors generates vectors from the kernel where each vector has the particular pixel as a central element. The normalizing values normalizes values for nearest neighbor elements to the central element for each vector. The determining an estimated value determines the value based on the normalized values.

Abstract: A method for finding and correcting single-pixel noise defects in a two-dimensional camera pixel field assigns to such pixel defect an interpolation multi-pixel environment of the same color as the pixel to be corrected for therefrom deriving an interpolated substitute pixel value. In particular, the method executes the following steps: assigns a multi pixel checking environment of the same color to a possibly defect pixel and checks the possibly defect pixel to the checking environment for finding a correct or an incorrect pixel assigns to an incorrect pixel a plurality of predictive multi-pixel environments each oriented in a respective different orientation with respect to the incorrect pixel for therefrom deriving respective viability characterizations for interpolation in the associated orientation finds the highest viability characterization and thereby selects an appropriate multi-pixel interpolation environment of the same color for actually interpolating a substitute pixel value.

Abstract: A viewfinder system for a digital camera comprises a main optical path for projecting an outside scene image onto a light sensitive area facility, which facility determines a user field, and an optical extraction path for through mirror-operation extracting a fraction of the outside scene image onto a viewer optical path. The viewer optical path comprises a first mask for inserting a negative delineating outline into a viewer field and a second mask for inserting a positive delineating outline into the viewer field, both said first and second masks corresponding to the user field. In particular, at least one of the first and second masks is realized by an electronic device that has its mask size variably controlled by an electronic facility on the basis of pixel-wise driving. Advantageously, the electronic device is controlled by a sensor facility that is adapted for with respect to the other of the masks that has a fixed size sensing the latter size.

Abstract: A charge-coupled imager includes an imaging section, a read-out section, and a way to reduce the number of charge packets for every row read. The imager is switchable between at least two read-out modes. The imaging section includes image elements arranged in a two-dimensional pattern. The read-out section includes at least a first horizontal CCD channel disposed beside the two-dimensional pattern, a second horizontal CCD channel and vertical CCD channels interlineated within the pattern of image elements. The imager is operable so that every image element of a row is individually readable in a first read-out mode using the first horizontal CCD channel comprising n charge storage locations. The imager is further operable in a second read-out mode so that a lower horizontal sampling frequency is read from the read-out section than in the first read-out mode using a second horizontal CCD channel comprising fewer storage locations than n.

Abstract: It is known to bring the surface into the inverted state in CCD imaging devices with buried channels during the integration period in order to keep the dark current low (All Gates Pinning). A desired potential profile, with wells in which the charge is integrated bounded by potential barriers, is obtained through, e.g. a doping profile in the channel. Line-shaped constrictions in the thickness or the doping concentration of the well enable charge-reset and function also as an anti-blooming barrier. In a charge coupled device according to the invention, the line-shaped constrictions in the thickness or the doping concentration of the second layer run perpendicular to the length direction of the channel and parallel to the gates and at least one line shaped constriction is positioned below each series of gates. In this way, an increased charge storage capacity and optical sensitivity are obtained while electronic shutter functionality is maintained.

Abstract: The present invention relates to an image recording device (10), comprising: an image section (11) with a number of picture elements (pixels) arranged in rows and columns; a storage section (12) with image storage elements arranged in rows and columns for (temporarily) at least partially storing charge absorbed by the pixels, wherein the charge is transferred to the storage elements; wherein one or more gates close to the transition (13) between the image section and the storage section are lengthened.

Abstract: A charge coupled imaging device includes a matrix of elements for converting an image projected onto the matrix into a frame of charge packets, along with a system of vertical charge transport channels (3) and a horizontal read-out register (C). A structure is provided for dumping unnecessary lines into a removal region in a certain operating mode. These lines are dumped at the transition between the imaging section and the memory section. The imaging device includes an imaging section (A) and a separate memory section (B) as well as a removal region (12) situated below the matrix as an anti-blooming provision. Unnecessary lines may be dumped, for example, into the substrate in that the transport in the imaging section is continued during frame transport while at the same time the transport in the memory section is stopped.

Abstract: The invention relates to a CCD of the buried-channel type comprising a charge-transport channel in the form of a zone (12) of the first conductivity type, for example the n-type, in a well (13) of the opposite conductivity type, in the example the p-type. In order to obtain a drift field in the channel below one or more gates (9, 10a) to improve the charge transfer, the well is provided with a doping profile, so that the average concentration decreases in the direction of charge transport. Such a profile can be formed by covering the area of the well during the well implantation with a mask, thereby causing fewer ions to be implanted below the gates (9, 10a) than below other parts of the channel. By virtue of the invention, it is possible to produce a gate (10a) combining a comparatively large length, for example in the output stage in front of the output gate (9) to obtain sufficient storage capacity, with a high transport rate.

Abstract: A charge coupled device has a hydrogen diffusion path to diffuse hydrogen to a silicon surface. The hydrogen diffusion path extends through a top silicon oxide layer that itself extends through a first aperture in a top silicon nitride layer. The first aperture overlays a conductor formed of polycrystalline silicon at a location that transversely overlays a channel stop. The hydrogen diffusion path extends through the conductor and through an extension of the conductor that itself extends through a second aperture in a lower silicon nitride layer. The lower silicon nitride layer being one part of a gate dielectric film. The gate dielectric film also includes a lower silicon oxide layer disposed between the lower silicon nitride layer and the silicon surface. The hydrogen diffusion path extends through the lower silicon oxide layer to reach the silicon surface.