Abstract: An aircraft-based power system includes at least one smart universal serial bus (USB-PD (Power Delivery)) outlet. The at least one smart universal serial bus (USB-PD (Power Delivery)) outlet being configured to connect to a power bus that receives power from a power source system. The at least one smart universal serial bus (USB-PD (Power Delivery)) outlet is further configured to control power delivery.

Abstract: Methods and systems of operating a computer system including a processor are disclosed. In one aspect, a method includes providing a discretized operating system for controlling applications executed by the computer system, and replacing an idle task of the discretized operating system with a substitute idle task that causes the processor to enter a dormant mode, a priority level of the substitute idle task being the same as a priority level of the idle task.

Abstract: Method and apparatus for maximizing the usable bandwidth for High Performance 1553 terminals operating concurrently on the same physical bus with legacy 1 Mb/s MIL-STD-1553 terminals. More specifically, the method and apparatus provides implementation for predictive cancellation by synthesizing an estimate of the 1 Mb/s MIL-STD-1553 component of a composite 1 Mb/s plus High Performance 1553 input signal using either of two different techniques: (1) a combination of digital and analog techniques; and (2) an all digital technique. The synthesized signal is then subtracted from the composite signal. Both techniques employ an algorithm for minimizing the effects of clock skew between 1 Mb/s 1553 transmitting clocks and the local High Performance 1553 sampling clock. Both techniques also incorporate an adaptation algorithm for developing and maintaining digital models of 1 Mb/s 1553 signals received from multiple 1 Mb/s 1553 terminals on a bus.

Abstract: Method and apparatus for maximizing the usable bandwidth for High Performance 1553 terminals operating concurrently on the same physical bus with legacy 1 Mb/s MIL-STD-1553 terminals. More specifically, the method and apparatus provides implementation for predictive cancellation by synthesizing an estimate of the 1 Mb/s MIL-STD-1553 component of a composite 1 Mb/s plus High Performance 1553 input signal using either of two different techniques: (1) a combination of digital and analog techniques; and (2) an all digital technique. The synthesized signal is then subtracted from the composite signal. Both techniques employ an algorithm for minimizing the effects of clock skew between 1 Mb/s 1553 transmitting clocks and the local High Performance 1553 sampling clock. Both techniques also incorporate an adaptation algorithm for developing and maintaining digital models of 1 Mb/s 1553 signals received from multiple 1 Mb/s 1553 terminals on a bus.

Abstract: Method and apparatus for maximizing the usable bandwidth for High Performance 1553 terminals operating concurrently on the same physical bus with legacy 1 Mb/s MIL-STD-1553 terminals. More specifically, the method and apparatus provides implementation for predictive cancellation by synthesizing an estimate of the 1 Mb/s MIL-STD-1553 component of a composite 1 Mb/s plus High Performance 1553 input signal using either of two different techniques: (1) a combination of digital and analog techniques; and (2) an all digital technique. The synthesized signal is then subtracted from the composite signal. Both techniques employ an algorithm for minimizing the effects of clock skew between 1 Mb/s 1553 transmitting clocks and the local High Performance 1553 sampling clock. Both techniques also incorporate an adaptation algorithm for developing and maintaining digital models of 1 Mb/s 1553 signals received from multiple 1 Mb/s 1553 terminals on a bus.

Abstract: A multi-dimensional Burst Link Access Streaming Transmission (BLAST) architecture, which provides flexible physical apparatus for balanced performance of data throughput, latency, and reliability of transmission (e.g. graceful degradation). A schedule is sent from a master node to alert targeted nodes regarding messages to be sent. The master node uses a P-Band transmission link operating a regular intervals to synchronize the system in preparation for receipt of a message over a synchronous link. Each node has the capability of sending and receiving synchronous and asynchronous messages.

Abstract: Method and apparatus for maximizing the usable bandwidth for High Performance 1553 terminals operating concurrently on the same physical bus with legacy 1 Mb/s MIL-STD-1553 terminals. More specifically, the method and apparatus provides implementation for predictive cancellation by synthesizing an estimate of the 1 Mb/s MIL-STD-1553 component of a composite 1 Mb/s plus High Performance 1553 input signal using either of two different techniques: (1) a combination of digital and analog techniques; and (2) an all digital technique. The synthesized signal is then subtracted from the composite signal. Both techniques employ an algorithm for minimizing the effects of clock skew between 1 Mb/s 1553 transmitting clocks and the local High Performance 1553 sampling clock. Both techniques also incorporate an adaptation algorithm for developing and maintaining digital models of 1 Mb/s 1553 signals received from multiple 1 Mb/s 1553 terminals on a bus.

Abstract: High density integrated circuits and more particularly to a high density integrated circuit incorporating a multiplicity of functional chips arranged on a substrate comprised of a plurality of dielectric and conductive layers which interface the semiconductor dies with a ball gate array (BGA) arranged on the underside of the substrate and wherein the main heat generating areas of the semiconductor dies are directly coupled to selected balls of the BGA for directly carrying heat from the major heat sources away from the device.

Abstract: Method and apparatus for interconnecting cards carrying heat generating ICs. A heat sink having a plurality of heat tubes is placed between two cards. The ICs are mounted “face down” so that the heat sink engages surfaces of the ICs opposite the surfaces having electrical and heat conductive terminals wherein an interstitial layer of a non-conducting, preferably gel-like material is placed between the heat sink and the surfaces of the ICs to alleviate mechanical stresses and enhance heat transfer. The thickness of the cards made of multiple conductive layers, separated by dielectric layers are controlled to provide cards of the same thickness. The heat sink provides proper spacing between and parallelism of facing surfaces of the cards to assure reliable connection and signal integrity between high speed connectors arranged on facing surfaces of the cards to electrically connect components from one board to the other.

Abstract: Method and apparatus for use of the dual redundant bus network utilizing time and frequency multiplexing techniques to provide a high bit rate system that maintains a lower bit error rate with good fault tolerance by sending a low speed message on one bus and a high speed message on the remaining bus then operating at a dual bus mode and for reducing the speed of the high speed to aerate between the high speed and low speed message rates and multiplexing the low speed and reduced high speed messages when a fault condition is detected on one of the buses. Techniques are provided for continuously monitoring the buses to identify the least recently used (LRU) to facilitate bus selection and selection of one of the dual bus and concurrent modes for operation.

Abstract: A power module with leads extending upwardly. The circuit components and connections of the power module are arranged upon a substrate having interface leads attached thereto extending away from the undersurface of the substrate. The interface leads extend through openings in a form fitting molded case. The case has an open center region to facilitate performance of final assembly steps upon the module and is subsequently covered with a rugged lid and is encapsulated with a suitable potting material. The interior of the module is filled with a gel to provide moisture-proof protection.

Abstract: A power module with leads extending upwardly. The circuit components and connections of the power module are arranged upon a substrate having interface leads attached thereto extending away from the undersurface of the substrate. The interface leads extend through openings in a form fitting molded case. The case has an open center region to facilitate performance of final assembly steps upon the module and is subsequently covered with a rugged lid and is encapsulated with a suitable potting material. The interior of the module is filled with a gel to provide moisture-proof protection.

Abstract: Apparatus for replacing conventional fault isolation resistors includes a terminal coupled to one winding of a transformer whose other winding is coupled across the two-line databus. Enhancement-mode-field-effect transistors have their source and drain electrodes each coupled between one end of the other winding and one of the databus lines and their control electrodes coupled at spaced intervals along the other winding. The winding voltage is zero when a terminal is not transmitting, turning off the field-effect transistors, presenting an open circuit. The parasitic body diodes of the transistors are connected in series and are poled to oppose each other to prevent conduction of signals from the databus. Thus, signals on the databus are not loaded by the terminal's output impedance. When winding voltage exceeds a threshold, one transistor conducts, providing substantially a short-circuit. The parasitic body diode of the remaining transistor also conducts.

Abstract: An integrated circuit device for comparing the state of a large number of inputs (i.e. "discretes") against any one of a plurality of selectable voltage levels. The compared data is examined in a 3.times.3 matrix format. In a redundant mode, comparators are utilized in a triple-redundant configuration to obtain a consensus on input states, at three successive time intervals, raising a flag when consensus fails. Inputs, whether in a redundant or non-redundant mode are distributed along three different sides of a rectangular-shaped substrate to prevent catastrophic mechanical failures. In the redundant mode, discretes are compared using a voting technique such that when all three levels are the same, an error free status is provided, whereas a two-out-of-three vote is interpreted as correct but with an indication that the discrete being monitored requires further checking.

Abstract: Apparatus for imparting a delay to an input signal utilizing counter means comprised of a plurality of binary coded decimal counter stages connected in cascade. The high frequency input signal applied to the counter undergoes a divide-by 10.sup.N operation wherein N equals the number of binary coded decimal stages. Preferably, the least significant stage is adapted to be selectively and periodically preset to a binary coded decimal value different from its normal reset state to either increase or reduce the number of pulses required to cause the counter stage to read a terminal count to selectively either advance or retard the phase of the reduced frequency output signal developed at the output of the counter relative to the phase of the input signal applied to the counter in accordance with a preprogrammed value set into said counter stage.

Abstract: An opto-video inspection system for inspecting and examining miniaturized solid-state devices, such as hybrids. An XY table simultaneously positions a known good device and a device to be inspected under respective stereo-zoom microscopes. A TV camera is coupled to each microscope. The XY table, under microprocessor control, is manipulated to select the "target" or wire bond to be viewed. The selected sites may be simultaneously viewed upon a split screen video display or, alternatively, either the known good device or the device being inspected may be separately viewed through the associated stereo-zoom microscope or on the video screen. Dwell time at each site is computer selectable, as is the sequencing of sites to be viewed. Defective bonds, imperfections or other conditions are permanently recorded through a printer which automatically associates the code printed thereby with the site in view at that time.

Abstract: A companding analog to digital converter for converting an analog signal into a variable length multi-bit binary word, the number of said bits being a function of the magnitude of the analog signal being converted relative to the high end of the range of magnitudes capable of being converted. The analog signal is temporarily stored and is attenuated by a predetermined amount. The attenuated signal is converted into a multi-bit digital word. A group of the most significant bits of said digital word are examined to alter the attenuation of the stored analog signal dependent upon its magnitude relative to the full scale. The attenuated analog signal is again converted into a multi-bit digital word which is temporarily stored. The group of binary bits initially stored together with results of the second conversion operation are combined to develop a multi-bit digital word whose bit length is a function of the magnitude of the stored analog signal relative to scale.

Abstract: A digital time phase shifter for shifting a signal in very precise increments and which performs the steps of: mixing a reference frequency signal with the signal to be time or phase delayed for generating an intermediate frequency signal; selectively delaying (i.e. advancing or retarding) the intermediate frequency signal; and mixing the delayed intermediate frequency signal and reference signal developing an output signal whose frequency is an integer multiple or sub-multiple of the input signal frequency and whose phase delay is proportional to the ratio of the intermediate signal and input signal frequencies. Small delay increments are obtained by judicious selection of the reference frequency. The output frequency may be slowly delayed relative to the input frequency by repeating the delay step. The phase shifter employs a pair of phase-locked loops, digital mixing circuits and a programmable delay generator.

Abstract: A hybrid solid state package in which integrated circuits, precision resistor networks, capacitors and their interconnections are accommodated on a multi-layer process substrate while thick film resistors and interconnections provided on a separate substrate, which sub-assemblies are then sandwiched together using film epoxies are inserted within a single package, to thereby yield a structure of significantly smaller size and lighter weight and having minimal number of input-output interconnections as compared with conventional designs and without impairing quality or reliability.