Abstract: An aircraft-based power system includes at least one smart universal serial bus (USB-PD (Power Delivery)) outlet. The at least one smart universal serial bus (USB-PD (Power Delivery)) outlet being configured to connect to a power bus that receives power from a power source system. The at least one smart universal serial bus (USB-PD (Power Delivery)) outlet is further configured to control power delivery.

Abstract: Methods and systems of operating a computer system including a processor are disclosed. In one aspect, a method includes providing a discretized operating system for controlling applications executed by the computer system, and replacing an idle task of the discretized operating system with a substitute idle task that causes the processor to enter a dormant mode, a priority level of the substitute idle task being the same as a priority level of the idle task.

Abstract: Method and apparatus for maximizing the usable bandwidth for High Performance 1553 terminals operating concurrently on the same physical bus with legacy 1 Mb/s MIL-STD-1553 terminals. More specifically, the method and apparatus provides implementation for predictive cancellation by synthesizing an estimate of the 1 Mb/s MIL-STD-1553 component of a composite 1 Mb/s plus High Performance 1553 input signal using either of two different techniques: (1) a combination of digital and analog techniques; and (2) an all digital technique. The synthesized signal is then subtracted from the composite signal. Both techniques employ an algorithm for minimizing the effects of clock skew between 1 Mb/s 1553 transmitting clocks and the local High Performance 1553 sampling clock. Both techniques also incorporate an adaptation algorithm for developing and maintaining digital models of 1 Mb/s 1553 signals received from multiple 1 Mb/s 1553 terminals on a bus.

Abstract: Method and apparatus for maximizing the usable bandwidth for High Performance 1553 terminals operating concurrently on the same physical bus with legacy 1 Mb/s MIL-STD-1553 terminals. More specifically, the method and apparatus provides implementation for predictive cancellation by synthesizing an estimate of the 1 Mb/s MIL-STD-1553 component of a composite 1 Mb/s plus High Performance 1553 input signal using either of two different techniques: (1) a combination of digital and analog techniques; and (2) an all digital technique. The synthesized signal is then subtracted from the composite signal. Both techniques employ an algorithm for minimizing the effects of clock skew between 1 Mb/s 1553 transmitting clocks and the local High Performance 1553 sampling clock. Both techniques also incorporate an adaptation algorithm for developing and maintaining digital models of 1 Mb/s 1553 signals received from multiple 1 Mb/s 1553 terminals on a bus.

Abstract: Method and apparatus for maximizing the usable bandwidth for High Performance 1553 terminals operating concurrently on the same physical bus with legacy 1 Mb/s MIL-STD-1553 terminals. More specifically, the method and apparatus provides implementation for predictive cancellation by synthesizing an estimate of the 1 Mb/s MIL-STD-1553 component of a composite 1 Mb/s plus High Performance 1553 input signal using either of two different techniques: (1) a combination of digital and analog techniques; and (2) an all digital technique. The synthesized signal is then subtracted from the composite signal. Both techniques employ an algorithm for minimizing the effects of clock skew between 1 Mb/s 1553 transmitting clocks and the local High Performance 1553 sampling clock. Both techniques also incorporate an adaptation algorithm for developing and maintaining digital models of 1 Mb/s 1553 signals received from multiple 1 Mb/s 1553 terminals on a bus.

Abstract: A multi-dimensional Burst Link Access Streaming Transmission (BLAST) architecture, which provides flexible physical apparatus for balanced performance of data throughput, latency, and reliability of transmission (e.g. graceful degradation). A schedule is sent from a master node to alert targeted nodes regarding messages to be sent. The master node uses a P-Band transmission link operating a regular intervals to synchronize the system in preparation for receipt of a message over a synchronous link. Each node has the capability of sending and receiving synchronous and asynchronous messages.

Abstract: Method and apparatus for maximizing the usable bandwidth for High Performance 1553 terminals operating concurrently on the same physical bus with legacy 1 Mb/s MIL-STD-1553 terminals. More specifically, the method and apparatus provides implementation for predictive cancellation by synthesizing an estimate of the 1 Mb/s MIL-STD-1553 component of a composite 1 Mb/s plus High Performance 1553 input signal using either of two different techniques: (1) a combination of digital and analog techniques; and (2) an all digital technique. The synthesized signal is then subtracted from the composite signal. Both techniques employ an algorithm for minimizing the effects of clock skew between 1 Mb/s 1553 transmitting clocks and the local High Performance 1553 sampling clock. Both techniques also incorporate an adaptation algorithm for developing and maintaining digital models of 1 Mb/s 1553 signals received from multiple 1 Mb/s 1553 terminals on a bus.

Abstract: High density integrated circuits and more particularly to a high density integrated circuit incorporating a multiplicity of functional chips arranged on a substrate comprised of a plurality of dielectric and conductive layers which interface the semiconductor dies with a ball gate array (BGA) arranged on the underside of the substrate and wherein the main heat generating areas of the semiconductor dies are directly coupled to selected balls of the BGA for directly carrying heat from the major heat sources away from the device.

Abstract: Method and apparatus for interconnecting cards carrying heat generating ICs. A heat sink having a plurality of heat tubes is placed between two cards. The ICs are mounted “face down” so that the heat sink engages surfaces of the ICs opposite the surfaces having electrical and heat conductive terminals wherein an interstitial layer of a non-conducting, preferably gel-like material is placed between the heat sink and the surfaces of the ICs to alleviate mechanical stresses and enhance heat transfer. The thickness of the cards made of multiple conductive layers, separated by dielectric layers are controlled to provide cards of the same thickness. The heat sink provides proper spacing between and parallelism of facing surfaces of the cards to assure reliable connection and signal integrity between high speed connectors arranged on facing surfaces of the cards to electrically connect components from one board to the other.

Abstract: Method and apparatus for use of the dual redundant bus network utilizing time and frequency multiplexing techniques to provide a high bit rate system that maintains a lower bit error rate with good fault tolerance by sending a low speed message on one bus and a high speed message on the remaining bus then operating at a dual bus mode and for reducing the speed of the high speed to aerate between the high speed and low speed message rates and multiplexing the low speed and reduced high speed messages when a fault condition is detected on one of the buses. Techniques are provided for continuously monitoring the buses to identify the least recently used (LRU) to facilitate bus selection and selection of one of the dual bus and concurrent modes for operation.