Abstract: A disk drive module adapted for use in a data processing system, the system including first and second disk drive module guide plates. The disk drive module comprises an elongated, generally rectangular frame. The top wall of the frame includes a fin slidably insertable into a groove formed on the second guide plate, and the bottom wall of the frame includes a T-bar slidably insertable into a channel formed on the first guide plate. The T-bar includes a detent which releasably engages a pawl formed in the channel for securing the T-bar within the channel. A 3.5 inch disk drive and a regulator card are mounted within the frame. The rear edge of the regulator card includes an edge connector which extends rearwardly beyond the frame a short distance. To ensure that the edge connector is properly guided into engagement with a corresponding electrical connector in the data processing system, the regulator card is mounted on the frame for movement in three directions.

Abstract: A data processing system is disclosed in which a plurality of high performance, intelligent, mass storage input-output devices are linked to a host controller by an input-output interface bus which is divided into three sections. Each section is completely independent of the other two sections and used for a different and specific purpose. One section is used to transfer commands and retrieve status information. A second section is used to handle device requests for data transfer and device signals for operation complete. The third section is used to transfer data to and from a device. Since the three sections are completely independent, simultaneous transfer of command control and data to different input-output devices or to a single input-output device can be performed.

Abstract: A method of assigning priorities and resolving bus contention in a distributed computer system is disclosed. Each system node is assigned an identifier. Priorities are reassigned at each change in bus access such that the node that most recently had access to the bus is assigned the lowest priority with the node having the next identifier in sequence being assigned the highest priority and all other nodes assigned priority in accordance with their identifier's position in the sequence. The identifiers are logically treated as organized in a circular fashion such that the lowest node identifier is considered to come next in the sequence after the highest node identifier.

Abstract: A data processing system having a local memory bus, a main memory coupled to the local memory bus and a host central processing unit coupled to the local memory bus includes a single input/output controller for interfacing a plurality of input/output devices to the local memory bus. The input/output controller includes a plurality of input/output device controllers, each input/output device controller being adapted to be connected to at least one input/output device, a single microprocessor for managing the overall operations of the input/output controller, a single buffer memory for storing a program of instructions for the microprocessor and temporarily storing data received from the input/output devices and a gate array for interfacing all of the input/output device controllers to the local memory bus.

Abstract: A data processing system which includes a central processing unit (CPU) to which is connected an I/O bus and a memory bus is disclosed. The data processing system further includes an I/O controller and a video control section. The I/O controller includes a terminal control section which is connected to the CPU through an RS232 Cable, an I/O control section which is connected to the I/O bus over a single line and a single processor for managing both the terminal control section and the I/O control section. The I/O control section includes a plurality of interface and control subsystems each for use with a separate peripheral device and an I/O bus interface and control subsystem. The terminal control section includes a video control section interface through which data is sent directly to the video control section over a separate line, and a keyboard interface for interfacing the terminal control section to a keyboard.

Abstract: A digital computer system having a memory system organized into procedure and data objects, each having a unique identifier code and an access control list, for storing items of information and a processor for processing data in response to instructions. The instructions contain operation codes and names representing data. Each name corresponds to a name table entry in a name table which contains information from which the processor determines the location and the format for the data. The name table entry specifies a base address of one of a set thereof which change value only when a call or a return instruction is executed. A name interpretation system fetches a name table entry, calculates the base address and a displacement using the name table entry and the current architectural base address and adds the base address to the displacement to form the address of the data represented by the name.

Abstract: Apparatus 117 interfaces system multiplexing/demultiplexing (MUX/DMUX) station circuitry 113, which exchanges pulse code modulated (PCM) signal samples of voice, data and control information in an interleaved port group format with a plurality of the system user ports 120 in each of a succession of sample time intervals, with the system time slot interchange (TSI) matrix 110 which switches the PCM voice, data and control signal samples in each sample time interval in groups of common signal type.

Abstract: Programmable feature card circuitry includes: a signal processor with parallel input/output (I/O) data ports and responsive to command of the PBX call processor, signal memory, and a signal interface for converting the PBX signal format to a processor compatible format; the signal memory including program memory for storing signal processor program signals representing the programmed algorithm to be performed by the signal processor in the execution of the user selected PBX support function and including data memory for storing data signals from the PBX, the signal processor executing the stored programmed algorithm in response to the command signals from the PBX call processor.

Abstract: A floating-point unit constructed of at least two identical modules. Each module contains registers for storing floating-point data, a sign and exponent processing unit for processing the sign and exponent portions of floating-point values, and a mantissa processing unit for processing the mantissa portion. Buses allow transfer of operands from the registers to the mantissa and sign and exponent processing units and the return of the result to the registers. Interconnections between the modules and configuration logic on each module enable the modules to function as a single floating-point unit. The interconnections include connections between corresponding buses of the modules and connections between corresponding mantissa processing units. The configuration logic is responsive to position signals indicating the module's position relative to other modules in the floating-point unit and precision signals indicating the precision of the floating-point data being processed by the unit.

Abstract: Method and apparatus for improving instruction decoding in a microcode-controlled digital computer system. The microinstruction sequences are made simple and compact enough that sufficient complexity is required in the instruction decoding logic that it is feasible to custom-configure a gate array to perform instruction decoding. The resultant gate array, by virtue of being embodied in a single integrated circuit, is extremely fast and compact and has low power requirements.

Abstract: A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a malfunction nibble shifter, and a high speed look-aside memory control.

Abstract: A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a multifunction nibble shifter, and a high speed look-aside memory control. Adaptive microcode control means 272 are disclosed in which microinstruction sequencing is a function 273 of the current microinstruction and current machine state.

Abstract: A data processing uses instructions which may refer to operands in main memory by either physical or logical addresses. The central processor has an internal memory organized as two portions. The first portion provides a scratchpad memory function for the central processor and the second portion is responsive to logical addresses to provide corresponding physical addresses.

Abstract: A content-addressable memory module which performs an associative clear operation in response to a clear signal provided on a clear line. The associative clear operation simultaneously clears all registers in the content-addressable memory module whose contents match bits in a pattern input to the content-addressable memory module. A mask input along with the pattern determines which bits of the pattern are significant for the match. Each register in the content-addressable memory module has a bidirectional match line associated with it. A register's bidirectional match line carries a match signal only if that register contains data matching the pattern bits specified by the mask and the bidirectional match line is receiving a match signal from an external source. Clearing logic associated with each register clears the register when a clear signal appears on the clear line while the register's bidirectional match line is carrying a match signal.

Abstract: Apparatus and methods for the calculation of addresses of data items in digital computer systems which perform call and return operations. In the digital computer systems of the invention, items of data called immediate names represent other items of data and specify how the address of the represented item is to be calculated. Certain immediate names represent items of data whose addresses are calculated using linkage pointers. Such an immediate name specifies the linkage pointer to be used in the calculation. Linkage pointers are pointers whose values remain unchanged during an execution of a procedure. When the digital computer system's processor executes the call operation, the processor places the addresses represented by the linkage pointers in internal registers.

Abstract: A system for performing operations on data items in digital computer systems in which the instructions may not specify internal registers in the processor as destinations of data received from memory or sources of data provided to memory. The system includes a result memory, apparatus for executing operations, instructions containing operation codes which specify that the result memory is to be a source of data to be operated on by the apparatus for executing operations, and control apparatus responsive to the operation codes for controlling the apparatus for executing operations. The result memory stores only the results of previous operations and may serve only as an input to the apparatus for executing instructions. The apparatus for executing operations may receive items to be operated on from either the computer system memory or the result memory.

Abstract: Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second cache and to the registers, and control apparatus connected to the first cache, the first multiplexer, and the second multiplexer. The first cache outputs a cache entry in response to a key. The cache entry contains a first displacement value, a base specifier specifying either one of the registers or the second cache, and in the case of entries specifying the second cache, a second displacement value. The first displacement value is output to the first multiplexer, the base specifier is output to the control apparatus, and the second displacement, if present, is output to the second cache.

Abstract: Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second cache and to the registers, and control apparatus connected to the first cache, the first multiplexer, and the second multiplexer. The first cache outputs a cache entry in response to a key. The cache entry contains a first displacement value, a base specifier specifying either one of the registers or the second cache, and in the case of entries specifying the second cache, a second displacement value. The first displacement value is output to the first multiplexer, the base specifier is output to the control apparatus, and the second displacement, if present, is output to the second cache.

Abstract: Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second cache and to the registers, and control apparatus connected to the first cache, the first multiplexer, and the second multiplexer. The first cache outputs a cache entry in response to a key. The cache entry contains a first displacement value, a base specifier specifying either one of the registers or the second cache, and in the case of entries specifying the second cache, a second displacement value. The first displacement value is output to the first multiplexer, the base specifier is output to the control apparatus, and the second displacement, if present, is output to the second cache.

Abstract: A computer network is disclosed in which a plurality of computer stations are interconnected by a single bi-directional bus and wherein access to the bus is controlled by the computer stations themselves through an adapter unit at each station. Each adapter unit includes a microcontroller, a transmitter, a receiver, a send buffer, a receive buffer, a line activity indicator, a pulse producing device, a read circuit and a write circuit. Each adapter unit has a unique assigned number. When the network is running and stable, control of the bus is continually passed from one live adapter unit to another in numerical sequence according to its unique assigned number and the bus is active with messages, control signals or status signals separated by relatively short intervals. If only one adapter unit is live, control is continually passed to itself.