Abstract: Apparatus and methods are disclosed for providing fast decoding of Reed-Solomon and related codes. Cases of one and two data symbol errors are decoded directly from the remainder using a large pre-computed table without calculating syndromes. Techniques for decoding cases of more than two errors are given where an optimized Chien search is used when more than four errors remain; when four or fewer errors remain, the Chien search is eliminated in favor of locating an error by direct solution of the error locator polynomial. The error locator and syndrome polynomials are adjusted after each error is found, and the error evaluator polynomial need not be computed.

Abstract: Disclosed is a serial encoder and time domain syndrome generator circuit utilized in a Reed-Solomon code application where the code has been defined with the conventional or standard representation of a finite field. The encoder will process k bits of an m-bit symbol per clock cycle, where 1.ltoreq.k.ltoreq.m and k evenly divides m. The encoder will process data in an interleave mode wherein data symbols of multiple codewords are interleaved in an interleaved data block. The encoder allows pipeline processing of register data within the encoder and time domain syndrome generator circuit to minimize circuit delay, and a linear network within the encoder is reduced in complexity by selecting a self-reciprocal code generator polynomial.

Abstract: Apparatus is disclosed for providing an improved encoder and frequency-domain syndrome generator circuit implementing Reed-Solomon codes which reduces hardware by sharing circuitry between the encoding and frequency-domain syndrome generation functions. Self-checking for proper encoder operation during write operations is achieved by verifying that all remainders from dividing codewords by factors of the code generator polynomial are equal to zero after encoding. Apparatus implements fast finite-field multiplication by a selected constant using Read Only Memory circuits. Hardware required is further reduced by incorporating Random Access Memory circuits and employing time-multiplexing techniques. Interleaved codewords are supported by implementing memory circuits for storing intermediate results of other codewords while processing symbols from one codeword.