Abstract: A computer based system for displaying and compressing video including a video capture card with a video compressor and a bus interface circuit that acts as a busmaster and outputs uncompressed video and compressed video to a computer bus for display of the uncompressed video on the computer monitor and storage of the compressed video on a memory of the computer.

Abstract: A PCMCIA card having an FPGA based card controller that is programmed with FPGA programming data stored on a host computer through a standard PCMCIA bus.

Abstract: An audio/video input/output (I/O) port apparatus for acquiring digital audio samples from one or multiple channels of input audio and synthesizing digital audio samples into one or multiple channels of output audio. The apparatus comprises a video I/O port, a frequency synthesizer, and an audio I/O port. The video I/O port generates a video-rate clock, and is configured to digitize input video into digital video, and to synthesize output video from digital video. The frequency synthesizer is configured to derive an audio sampling clock based on the video-rate clock. The audio I/O port is configured to sample input audio and convert it into digital audio samples according to the sampling clock, and to synthesize digital audio samples into output audio according to the sampling clock. The apparatus ensures that the video and audio data track together, both when inputting the information from an external source and when outputting the audio/video data streams.

Abstract: A video peripheral board for providing video I/O capabilities to a general purpose host computer. The video peripheral board comprises a video I/O port configured to connect a video device, a bus interface circuit, and a processor. The bus interface circuit is configured to connect the video peripheral board into a system bus of the host computer, and is capable of becoming bus master of the system bus. The bus interface circuit includes a bus master address generator, a data buffer and bus control logic that provides and receives bus control signals to and from the system bus to effect read and write operations over the system bus independent of the central processing unit of the host computer. The processor controls the bus interface circuit and the video I/O port to effect transfer of video data between the video I/O port and storage of the host computer, the video data passing through the video I/O port in real time.

Abstract: Apparatus for displaying a reduced-size image in a window of the display of a host computer, the reduced-size image based upon subsampled digital image data. The apparatus includes a host computer and a peripheral controller. The peripheral controller includes a subsampler that receives digital source image data and outputs subsampled image data, and window display circuit. The window display circuit receives a directive from the host computer indicating a window location on the host's display, and the subsampled image data. The window display circuit autonomously (independently of the host CPU) writes the subsampled data through the host's system bus into the display memory at addresses corresponding to the specified window. The apparatus allows video to be displayed on the display screen while avoiding intensive involvement or supervision by the host CPU during display of the video image data.

Abstract: Apparatus for storing interlaced video data in a split video memory in noninterlaced form in real video time and without wasted RAM space through the use of a video memory controller that controls transfers between a serial access memory (SAM) including a lower SAM (LSAM) and upper SAM (USAM) and a random access memory (RAM) including a lower RAM (LRAM) and an upper RAM (URAM) of the video memory during free time between video lines when pixel data are not being received, the video memory controller transmitting transfer control signals to the video memory to cause data stored in the LSAM and USAM to be written to the proper page location in the LRAM and URAM after a line has been written in order to save the data before receiving the next line, the controller also generating transfer control signals to cause data in the LRAM and URAM to be read back into the LSAM and the USAM before receiving new data in order to save data that may have already been written into the same page (e.g.

Abstract: A data acquisition circuit for receiving an analog input signal having a magnitude representing light intensity detected by a sequentially accessed, linear array of photocells of a line scan camera and providing digital data signals for use by a computer, the circuit including an analog-to-digital converter to convert said analog input signal to a stream of digital intensity signals, an offset memory storing offset correction values for respective photocells, a gain memory storing gain correction values for respective photocells, an adder connected to add or subtract the digital intensity signal for a given photocell to the offset correction value for that photocell and provide an offset-corrected digital signal, a multiplier connected to multiply the offset-corrected digital signal for a given photocell times the gain correction value for that photocell to provide a calibrated digital signal. Also disclosed are: comparing, on a photocell-by-photocell (i.e.

Abstract: An oscillator including an oscillator input node for receiving an oscillator input analog signal, an oscillator output node for providing a train of output pulses having a frequency related to the magnitude of the input analog signal, a trigger gate component connected between the input node and the output node and having a low threshold and a high threshold, the gate component being in a path between the input and output without other active components and having a low input current in the range of 1 uA or less, a feedback switch connected in parallel to the trigger gate component and having a switch turn on threshold such that the switch is turned on to conduct current when the trigger gate is in one output state and is turned off when the trigger gate is in the other output state, and capacitance between a reference voltage and the input node so that the voltage at the input node ramps from one threshold to the other at a rate dependent on the input current.

Abstract: A circuit for converting input analog signals to output digital signals including an analog-to-digital converter having an analog input, an offset input and a digital output that represents the value of a signal at the analog input offset by an amount related to the value of the signal at the offset input, signal conditioning circuitry for receiving the input analog signal and providing it to the analog input via one of a plurality of different paths or under one of a plurality of different conditions, the different paths or different conditions providing different offsets to the input analog signal, and an offset correction memory storing offset correction characteristics for respective paths or conditions and being connected to provide an offset signal based on the characteristic for a path or condition to the offset input.

Abstract: Circuitry for converting digital red, green, blue (RGB) inputs into digital saturation and hue outputs comprising hardwired digital components connected to receive the digital RGB inputs and to perform arithmetic manipulations of them so as to provide a digital saturation output representing saturation for the RGB inputs and to provide a digital first intermediate output, and a first look-up memory storing digital hue data representing hue of the digital RGB inputs at addresses corresponding to values of the digital first intermediate output, the look-up memory being connected to the hardwired digital components to be addressed by the digital intermediate output, the memory providing a digital hue output.

Abstract: An apparatus for controlling sequential (DMA) transfers between a plurality of buffer memories and a data translation device. Each buffer has an overrun has an overrun area associated with it. Prior to transfers from the buffers to the data translation device, the buffer memories are first "threaded" together by loading the overrun area of a first buffer with data from the next buffer. During the DMA transfer, when the first buffer becomes empty a request is made to the computer to restart the DMA operation on the next sequential buffer, but while the interrupt is being serviced data is continually being transferred out of the first buffer's overrun area. Alternatively, for transfers from the data translation device to the buffers, after the first buffer is full, an interrupt is generated and incoming data is stored in the first buffer's overrun area while the interrupt is being serviced. After the interrupt is serviced data is stored in the next sequential buffer.

Abstract: Apparatus controls sequential direct memory access (DMA) transfers between a plurality of buffer memories and a data translation device. Each buffer memory has an overrun area associated with it. Prior to transfers from the buffer memories to the data translation device, the buffer memories are first "threaded" together by loading the overrun area of a first buffer memory with data from the next buffer memory. During the DMA transfer, when the first buffer memory becomes empty a request is made to a computer to restart the DMA operation on the next sequential buffer, but while the request is being serviced, data is continually being transferred out of the first buffer's overrun area. Alternatively, for transfers from the data translation device to the buffer memories, after the first buffer memory is full, an interrupt is generated and incoming data is stored in the first buffer memory's overrun area while the interrupt is being serviced.

Abstract: A data acquisition circuit is disclosed which provides sampled input voltage signals generated in a hostile environment to an input device, for example, the input circuitry of a computer. The data acquisition circuit provides electrical isolation to prevent damage to the input circuitry caused by electrical transients and short circuits occurring in the hostile environment and is particularly useful for sampling input data from thermocouples because it eliminates the need for an isolated power supply normally used to detect broken thermocouples.