Abstract: Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access time. In one embodiment, the primary systems of the disk emulator are a 66-bit shift register, a parity circuit, a latch circuit, a 66-bit parallel bus and a dynamic random access memory (DRAM) array. Each of these systems interface with control systems of the disk emulator which provide the signals required for the read and write operations of the disk emulator. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit.

Abstract: Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access time. In one embodiment, the disk emulator includes a volatile storage medium, a parallel path, a nonvolatile media and a control circuit. The control circuit can store parallel data received on the parallel path into the nonvolatile media and supply parallel data from the nonvolatile storage media on the parallel path. Moreover, in a first mode of operation the control circuit can store data received from a disk controller at a location in the volatile storage medium and in a second mode of operation, the control circuit can retrieve data from the volatile storage medium and provide the retrieved data to the disk controller.