Abstract: A computer system which assigns a unique identifier to each component in the system. The system includes a microprocessor, a memory, and one or more components. The microprocessor and the memory are coupled by first data lines. Each component has a storage device for storing data to uniquely identify each component and second data lines, the second data lines coupled to the first data lines. The storage device includes an identification input which is coupled to a selected one of the second data lines. The storage device in each component stores data from the selected one of the second data lines during the transmission of a sequence of data from the memory on the second data lines. With the system, a unique and consistent identifier can be assigned to each component in a computer system, each time the computer system is started. A separate memory device to store an identifier for each component is unnecessary.

Abstract: An apparatus to permit the sharing of interrupts between resident devices and removable PCMCIA peripherals overcomes a deficiency in the PCMCIA standards. By permitting interrupt sharing, the apparatus allows standard application software, which assumes the interrupt sharing capability of standard built-in peripherals to operate with PCMCIA cards. The invention is particularly suited to serial communication ports, where interrupts are routinely shared. An interface component 20 is coupled to an interrupt controller 12. A serial port COM1 is connected to a host interrupt IRQ4, which is shared by a PCMCIA card serial port 22, configured as COM3, through the interface controller 20. Through the use of an open-drain output and a conversion in the controller 20 of the level mode interrupt from the PCMCIA card to a low-going pulse of sufficient voltage swing and duration, the host interrupt is shared between the permanently installed COM1 and the removable COM3 serial ports.

Abstract: The ability to stop a clock in a CMOS peripheral device or other CMOS IC, and reliably restart it based on an asynchronous event, provides the basis for considerable power savings. In a computer system 20 an interface component 10 has a clock restart circuit 100. The restart circuit 100 includes a series of D-type CMOS flip-flops (110, 112, 118) that are initially set in their zero state. A logic OR gate 120 receives the microprocessor clock and the complimentary output of the last flip-flop to provide a reliable, restarted clock signal for the interface component 10 and its peripherals 26.