Abstract: An integrated support tool set that allows a programmer to design an efficient pipelined FPGA.

Abstract: A streaming memory controller has a time-division multiplexed interface to sources and destinations of data and a streaming interface to a memory. A unified address generator with look-aside registers is used to provide addresses for the memory. Each source and destination is identified by a context code that is used to index into a table of parameters. A processor loads initial values for the parameters that are then used by the unified address generator to access the appropriate area of memory for the context. Buffers hold data for read and write contexts. An arbiter specifies the context having the greatest requirement for memory access based on the context's buffer status. A sequencer sends streams of data for a specified context to memory until the interrupted by the arbiter.

Abstract: A system for digital image recognition which combines sparse correlation with image pyramiding to reduce the number of pixels used in correlation provides effective recognition of a reference image template without exhaustive correlation of all pixels in the reference image template. An optimal sparse pixel set is selected from the pixels of the reference image template by correlating the reference image template against a search image scene which is to be searched. Such a sparse pixel set includes those pixels which are optimal in defining the correlation sensitive features of the reference image template. By terminating the accumulation of sparse pixels at an optimal point, performance is maximized without compromising accuracy of recognition. The resultant optimal sparse pixel set is then correlated against the pixels in the search image scene through a series of transformations to find a match of the reference image template within the search image scene.

Abstract: A web inspection system for analysis of a moving web of material records and stores continuous sequences of the web. The web inspection system includes a camera for recording the continuous sequence of the web, an encoder for synchronizing movements of the web with the video image being recorded, and an Image Processing System (IPS) including a real time video disk for storing the image of the web and for displaying the continuous sequence web image on a video display. The IPS is also utilized for detecting faults or features and for categorizing the faults or features detected. The entire web is recorded and the image can be viewed either interactively while the image is being recorded or at a later time. The recorded image of the web can be played back at a slower speed to allow for a more detailed inspection of the web. The sequence image can be analyzed to build a defect image database. The web inspection system can also be utilized for sorting and displaying defect information.

Abstract: The invention provides a method and apparatus for performing image data compression. Initially, a two-dimensional block of image data in a spatial domain is transformed by a transform coder, resulting in a two-dimensional array of activity coefficients in a frequency domain. The array is then serialized and quantized, yielding a one-dimensional array of coefficients with a leading coefficient and an original trailing coefficient. Next, a portion of the array is selected by choosing a new trailing coefficient based on a setable ratio of the energy of the new short array to the energy of the original array. Lastly, an end-of-block symbol is appended after the new trailing coefficient, and the selected portion of the array is encoded using an entropy coder. The invention allows image data to enjoy enhanced compression with good image fidelity, and allows image fidelity to degrade gracefully in trade for higher degrees of image compression.