Abstract: A memory subsystem and method for loading and storing data at memory addresses of the subsystem. The memory subsystem is functionally connected to a processor and has a first mode of address encryption to convert logical memory addresses generated by the processor into physical memory addresses at which the data are stored in the memory subsystem. The memory subsystem is adapted to pull low a write enable signal to store data in the memory subsystem and to pull high the write enable signal to load data in the memory subsystem, wherein if pulled high the write enable signal alters the address encryption from the first mode to a second mode. The memory subsystem is adapted to be coupled to a local hardware device which supplies a key that acts upon the address encryption of the memory subsystem.

Abstract: A method and architecture that overcomes the problem of latency-caused performance degradation of electronic memory systems. The method involves a “Posted Precharge,” by which an external command for Precharge is given as early as possible, such as immediately following a Read command. The execution of the Precharge is delayed by a precharge counter until all Read/Write commands are completed. By posting a precharge command on a bus at the first available opportunity, multiple pages can be open on the same bank of a memory device. As a result, access latencies are significantly reduced and efficiency of bus in electronic memory systems is significantly improved.