Abstract: In a telecommunications switching system, the physical switching matrix is constructed in modular parts for easy expansion. A complete set of switching lines in one direction is cross-indexed with a partial set of switching lines in the other direction, and modular expansion is allowed by adding further partial sets of switching lines to further complete the matrix. Minimum bit delay is accomplished by routing all data bits through at most two data buffers on their transmission through the switch.

Abstract: In a telecommunication switching system, a communication link between distant devices is allocated in a quasi-TDMA (time division multiple access) manner between two distant devices. Messages are conformed to a data format which allows the switching center to determine in which direction data is to be transmitted, within at most a few bit transmission times. Both half-duplex and full-duplex communication links are possible.

Abstract: In an telecommunications switching system, user clock data is "massively sampled" at the source node with reference to a global clock signal, and reconstructed with no more than allowable error at the destination. Massive sampling and reconstruction of the clock signal allows users of the transmission system to send data at arbitrary data rates and to perform their own clock synchronization at a different protocol level from the hardware switching system. Direct use of the global system clock rate of approximately 192 kilobits per second (kbps) is provided for by synchronizing the user data with the global clock signal.