Abstract: A memory area managing method of a multi-port memory device in a memory link architecture which includes a multi-port memory device, a memory controller, and a flash memory, the method including performing a data processing step in which data stored in a host CPU area of the multi-port memory device is processed by a host CPU connected with the multi-port memory device, the processed data being stored in a shared area; performing a file data generating step in which file data on the processed data stored in the shared area is generated according to a write command of the host CPU, the file data being stored in a memory controller area of the multi-port memory device; and performing a file data storing step in which the file data is read out from the memory controller area and the read file data is sent to the flash memory.

Abstract: A system and method that transfers data from a ROM writer to memory socket assemblies (MSAs), each MSA capable of mechanically mounting and thereby electrically connecting a memory link architecture (MLA) and including a memory and a control device. Only after transferring the data from the ROM writer to at least one of the plurality of MSA but before mounting a corresponding MLA in each one of the plurality of MSAs, data is written from a memory in one MSA to a corresponding nonvolatile memory.

Abstract: A memory link architecture (MLA) comprises a multi-port memory device, a memory controller, and a nonvolatile memory. The MLA can perform a sleep switching control operation or a memory management operation to reduce power consumption based on commands received from a host processor and/or automatic control methods.

Abstract: A multi-chip package test apparatus is for testing a plurality of semiconductor packages including a plurality of flash memories and an application specific integrated circuit (ASIC) stacked on a single substrate. The multi-chip package test apparatus includes a plurality of test sockets configured to receive the plurality of semiconductor packages, respectively, a plurality of central processing units (CPUs) mounted on a test board and each configured to execute a package test of a respective one of the semiconductor packages received by the plurality of sockets, and a plurality of multiple access dynamic random access memory (DRAM) device operatively interposed between the CPUs and test sockets, respectively, each of the multiple access DRAM devices configured with separate memory areas for access by a respective CPU and a respective ASIC of the semiconductor packages.