Abstract: A charge pump and operating method thereof are disclosed. The charge pump includes a first capacitor to a third capacitor and a first switch to a tenth switch. The charge pump is used to receive an input voltage and provide an output voltage to a load capacitor. When the charge pump is operated in a first mode, the charge pump controls the second capacitor failure, the output voltage and the input voltage have opposite electricity and the output voltage is (?½) times the input voltage. When the charge pump is operated in a second mode, the charge pump controls the second capacitor failure, the output voltage and the input voltage have opposite electricity and the output voltage is (??) times the input voltage.

Abstract: A driving chip set includes a master chip and at least one slave chip. In the master chip, a master receiving terminal receives a data signal through a first data transmission interface; a processing unit generates a first partial data signal and a second partial data signal according to the data signal; a master buffer registers the first partial data signal; a master output terminal outputs the second partial data signal through a second data transmission interface. In the slave chip, a slave receiving terminal receives the second partial data signal through the second data transmission interface and it is registered by a slave buffer. The processing unit controls a master driver and a slave driver to output the first partial data signal and second partial data signal to a display panel. The display panel displays an image according to the first partial data signal and second partial data signal.

Abstract: A driving chip set includes a master chip and at least one slave chip. In the master chip, a master receiving terminal receives a data signal through a first data transmission interface; a processing unit generates a first partial data signal and a second partial data signal according to the data signal; a master buffer registers the first partial data signal; a master output terminal outputs the second partial data signal through a second data transmission interface. In the slave chip, a slave receiving terminal receives the second partial data signal through the second data transmission interface and it is registered by a slave buffer. The processing unit controls a master driver and a slave driver to output the first partial data signal and second partial data signal to a display panel. The display panel displays an image according to the first partial data signal and second partial data signal.