Abstract: Method to extract timing diagrams from synchronized single- or two-photon pulsed LADA by spatially positioning the incident laser beam on circuit feature of interest, temporally scanning the arrival time of the laser pulse with respect to the tester clock or the loop length trigger signal, then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time. A Single-Photon Laser-Assisted Device Alteration apparatus applies picosecond laser pulses of wavelength having photon energy equal to or greater than the silicon band-gap. A Two-Photon Laser-Assisted Device Alteration apparatus applies femtosecond laser pulses of wavelength having photon energy equal to or greater than half the silicon band-gap at the area of interest. The laser pulses are synchronized with test vectors so that pass/fail ratios can be altered using either the single-photon or the two-photon absorption effect. A sequence of synthetic images with error data illustrates timing sensitive locations.

Abstract: Method to extract timing diagrams from synchronized single- or two-photon pulsed LADA by spatially positioning the incident laser beam on circuit feature of interest, temporally scanning the arrival time of the laser pulse with respect to the tester clock or the loop length trigger signal, then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time. A Single-Photon Laser-Assisted Device Alteration apparatus applies picosecond laser pulses of wavelength having photon energy equal to or greater than the silicon band-gap. A Two-Photon Laser-Assisted Device Alteration apparatus applies femtosecond laser pulses of wavelength having photon energy equal to or greater than half the silicon band-gap at the area of interest. The laser pulses are synchronized with test vectors so that pass/fail ratios can be altered using either the single-photon or the two-photon absorption effect. A sequence of synthetic images with error data illustrates timing sensitive locations.

Abstract: Current Voltage and Capacitance Voltage (IV and CV) measurements are critical in measurement of properties of electronic materials especially semiconductors. A semiconductor testing device to accomplish IV and CV measurement supports a semiconductor wafer and provides a probe for contacting a surface on the wafer under control of an atomic Force Microscope or similar probing device for positioning the probe to a desired measurement point on the wafer surface. Detection of contact by the probe on the surface is accomplished and test voltage is supplied to the semiconductor wafer. A first circuit for measuring capacitance sensed by the probe based on the test voltage and a complimentary circuit for measuring Fowler Nordheim current sensed by the probe based on the test voltage are employed with the probe allowing the calculation of characteristics of the semiconductor wafer based on the measured capacitance and Fowler Nordheim current.

Abstract: Milling using a scanning probe microscope with a diamond tip removes a layer of material and produces a surface that is sufficiently smooth that it can be probed using a nanoprober to provide site-specific sample preparation and delayering. Diamond milling provides in situ, localized, precision delayering inside of a nanoprobing tool, thereby decreasing the turnaround time for integrated circuit analysis. Furthermore, unlike focused ion beam delayering, the diamond tip should not alter the electrical characteristics of the integrated circuit.

Abstract: A charged particle beam, such as an electron beam or an ion beam, scans a device while a signal is applied to the device. As the particle beam scans, it locally heats the device, altering the local electrical characteristics of the device. The change in electrical characteristic is detected to and correlated to the position of the electron beam to localize a defect.

Abstract: A system for performing sample probing. The system including an topography microscope configured to receive three-dimensional coordinates for a sample based on at least three fiducial marks; receive the sample mounted in a holder; and navigate to at least a location on the sample based on the at least three fiducial marks and the three-dimensional coordinates.

Abstract: Using a local-potential-driving probe drives a conductor to a known potential while adjacent lines are grounded through the sample body reduces electrostatic scanning microscope signal from adjacent lines, allows imaging of metal lines deeper in the sample. Providing different potentials locally on different conductive lines using multiple local-potential-driving probes allows different conductors to be highlighted in the same image, for example, by changing the phase of the signal being applied to the different local-potential-driving probes.

Abstract: A method of obtaining two orthogonally polarized super-resolution images is provided. A first diffraction-limited image is obtained using horizontally polarized light; a second diffraction-limited image is obtained using vertically polarized light; and, the first and second images are processed so as to yield a convoluted image having super diffraction-limited performance in both dimensions. Enhanced alignment of CAD image to acquired image is facilitated using the horizontally and vertically polarized images.

Abstract: A non-destructive approach for the 3D localization of buried hot spots in electronic device architectures by use of Lock-in Thermography (LIT). The 3D analysis is based on the principles of thermal wave propagation through different material layers and the resulting phase shift/thermal time delay. With more complex multi level stacked die architectures it is necessary to acquire multiple LIT results at different excitation frequencies for precise hot spot depth localization. Additionally, the use of multiple time-resolved thermal waveforms, measured in a minimized field of view on top of the hot spot location, can be used to speed up the data acquisition. The shape of the resulting waveforms can be analyzed to further increase the detection accuracy and confidence level.

Abstract: An apparatus and method for laser probing of a DUT is disclosed. The system enables laser voltage imaging state mapping of devices within the DUT. A selected area of the DUT is illuminating a while the DUT is receiving test signals causing certain of the active devices to modulate. Light reflected from the DUT is collected and is converted into an electrical signal. Phase information is extracting from the electrical signal and a two-dimensional image is generated from the phase information, wherein the two-dimensional image spatially correlates to the selected area.

Abstract: An apparatus for providing modulation mapping is disclosed. The apparatus includes a laser source, a motion mechanism providing relative motion between the laser beam and the DUT, signal collection mechanism, which include a photodetector and appropriate electronics for collecting modulated laser light reflected from the DUT, and a display mechanism for displaying a spatial modulation map which consists of the collected modulated laser light over a selected time period and a selected area of the IC.

Abstract: A pulsed-laser LADA system is provided, which utilizes temporal resolution to enhance spatial resolution. The system is capable of resolving CMOS pairs within the illumination spot using synchronization of laser pulses with the DUT clock. The system can be implemented using laser wavelength having photon energy above the silicon bandgap so as to perform single-photon LADA or wavelength having photon energy below the silicon bandgap so as to generate two-photon LADA. The timing of the laser pulses can be adjusted using two feedback loops tied to the clock signal of an ATE, or by adjusting the ATE's clock signal with reference to a fixed-pulse laser source.

Abstract: Controlled amount of heat is injected into a stacked die using a light beam, and the propagated heat is measuring with LIT camera from the other side of the die. The thermal image obtained can be characterized so that it can be used to calibrate the phase shift from a given stack layer, or can be used to identify defects in the stacked die. The process can be repeated for each die in the stack to generate a reference for future testing. The thermal image can be investigated to detect faults, such as voids in vias, e.g., TSV.

Abstract: In one embodiment, a method for aligning an image of a semiconductor device with a bitmap representation thereof includes receiving diffusion layer information of at least a portion of the semiconductor device, receiving implant layer information of the at least a portion of the semiconductor device, deriving distinct p- and n-doped region information from the received diffusion and implant layer information, generating the bitmap representation, including a differentiation between the distinct p- and n-doped regions, and performing an alignment operation of the image of the semiconductor device with generated bitmap representation.

Abstract: A system for analyzing a sample is described. The system for analyzing a sample includes a probe and a controller circuit. The controller circuit configured to control a movement of the probe to at least a first position and a second position on the sample based on navigation data. In response to the movement of the probe, the controller circuit is configured to adjust a force of the probe on the sample at the first position from a first force value to a second force value and the force of the probe on the sample from a third force value to a fourth force value at said second position on the sample. And, the controller circuit is configured to acquire sample data with the probe at the first position on the sample.

Abstract: A system for analyzing a sample is described. The system for analyzing a sample includes a probe and a controller circuit. The controller circuit configured to control a movement of the probe to at least a first position and a second position on the sample based on navigation data. In response to the movement of the probe, the controller circuit is configured to adjust a force of the probe on the sample at the first position from a first force value to a second force value and the force of the probe on the sample from a third force value to a fourth force value at said second position on the sample. And, the controller circuit is configured to acquire sample data with the probe at the first position on the sample.

Abstract: Controlled amount of heat is injected into a stacked die using a light beam, and the propagated heat is measuring with LIT camera from the other side of the die. The thermal image obtained can be characterized so that it can be used to calibrate the phase shift from a given stack layer, or can be used to identify defects in the stacked die. The process can be repeated for each die in the stack to generate a reference for future testing. The thermal image can be investigated to detect faults, such as voids in vias, e.g., TSV.

Abstract: A method for emission testing of a semiconductor device (DUT), by mounting the DUT onto an test bench of an emission tester, the emission tester having an optical detector; electrically connecting the DUT to an electrical tester; applying electrical test signals to the DUT while keeping test parameters constant; serially inserting one of a plurality of shortpass filters into an optical path of the emission tester and collecting emission test signal from the optical detector until all available shortpass filters have been inserted into the optical path; determining appropriate shortpass filter providing highest signal to noise ratio of the emission signal; inserting the appropriate shortpass filter into the optical path; and, performing emission testing on the DUT.

Abstract: A method for calculating a centreline of an object is disclosed. An image of the object is divided into test areas. For each test area, detection direction and scanning direction are assigned from a list of limited directions. For each test area, at each scanning point a local point of the centreline is determined along the detection direction. An assigned smoothing function is applied to the collection of local points to determine the collection of pixels which define the centreline. The collection of pixels can be used to calculate the length of the centreline. Also, the coordinates of the pixels of the centreline can be used to average the intensity of the image along the centreline.

Abstract: A non-destructive approach for the 3D localization of buried hot spots in electronic device architectures by use of Lock-in Thermography (LIT). The 3D analysis is based on the principles of thermal wave propagation through different material layers and the resulting phase shift/thermal time delay. With more complex multi level stacked die architectures it is necessary to acquire multiple LIT results at different excitation frequencies for precise hot spot depth localization. Additionally, the use of multiple time-resolved thermal waveforms, measured in a minimized field of view on top of the hot spot location, can be used to speed up the data acquisition. The shape of the resulting waveforms can be analyzed to further increase the detection accuracy and confidence level.