Patents Assigned to DECA TECHNOLOGIES INC.
-
Patent number: 8826221Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.Type: GrantFiled: May 13, 2013Date of Patent: September 2, 2014Assignee: DECA Technologies Inc.Inventors: Christopher M. Scanlan, Timothy L. Olson
-
Publication number: 20140225271Abstract: Panelized packaging is described in which a plurality of die units are placed on a dielectric film. The dielectric film is then cured to lock the plurality of die unit in place, which are then encapsulated. The cured dielectric film is then patterned utilizing a mask-less pattering technique.Type: ApplicationFiled: April 24, 2014Publication date: August 14, 2014Applicant: DECA Technologies Inc.Inventor: Christopher M. Scanlan
-
Patent number: 8799845Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.Type: GrantFiled: September 7, 2010Date of Patent: August 5, 2014Assignee: Deca Technologies Inc.Inventors: Christopher M. Scanlan, Timothy L. Olson
-
Patent number: 8784621Abstract: A wafer carrier is described. In one embodiment, the wafer carrier includes a variable aperture shield.Type: GrantFiled: September 30, 2011Date of Patent: July 22, 2014Assignee: DECA Technologies Inc.Inventor: Rico Sto. Domingo
-
Patent number: 8656333Abstract: A plurality of approaches for forming a semiconductor device using an adaptive patterning method is disclosed. Some approaches include placing a semiconductor die unit on a carrier element, calculating trace geometry for a second set of traces, constructing a prestratum comprising a first set of traces, and constructing the second set of traces according to the calculated trace geometry. Forming the semiconductor device may further include electrically connecting at least one of the first set of traces to at least one of the second set of traces, and electrically connecting at least one bond pad of the semiconductor die unit to a destination pad through the at least one of the first set of traces and the at least one of the second set of traces.Type: GrantFiled: May 7, 2012Date of Patent: February 18, 2014Assignee: Deca Technologies, Inc.Inventors: Craig Bishop, Christopher Scanlan, Tim Olson
-
Publication number: 20140008809Abstract: A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer.Type: ApplicationFiled: September 12, 2013Publication date: January 9, 2014Applicant: Deca Technologies, Inc.Inventor: Christopher M. Scanlan
-
Patent number: 8604600Abstract: A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap.Type: GrantFiled: December 30, 2011Date of Patent: December 10, 2013Assignee: DECA Technologies Inc.Inventor: Christopher M. Scanlan
-
Publication number: 20130280826Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. A plurality of semiconductor die comprising a copper column disposed over the active surface of each semiconductor die is provided. An embedded die panel is formed by disposing an encapsulant around each of the plurality of semiconductor die. A true position and rotation of each semiconductor die within the embedded die panel is measured. A unit-specific pattern is formed to align with the true position of each semiconductor die in the embedded die panel. The unit-specific pattern as a fan-out structure disposed over the semiconductor die, over the encapsulant, and coupled to the copper columns. A fan-in redistribution layer (RDL) can extend over the active surface of each semiconductor die such that the copper columns formed over the fan-in RDLs. The unit-specific pattern can be directly coupled to the copper columns.Type: ApplicationFiled: May 9, 2013Publication date: October 24, 2013Applicant: DECA Technologies Inc.Inventor: DECA Technologies Inc.
-
Publication number: 20130248361Abstract: A wafer carrier is described. In one embodiment, the wafer carrier includes a variable aperture shield. The wafer carrier may include an electrically conductive wafer plating jig base having a plurality of concentric overlapping cavities of different depths, each cavity configured to receive a semiconductor wafer of a different size, a plurality of concentric magnetic attractors, at least one positioned within each of the plurality of overlapping cavities, and a cover plate comprising an open center surrounded by a support, the cover plate comprising an attractive material positioned within the support adjacent to the open center and aligned with at least one of the magnetic attractors when the cover plate is positioned over the wafer plating jig base.Type: ApplicationFiled: May 16, 2013Publication date: September 26, 2013Applicant: DECA Technologies IncInventor: Rico Sto. Domingo
-
Publication number: 20130249088Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.Type: ApplicationFiled: May 13, 2013Publication date: September 26, 2013Applicant: DECA Technologies Inc.Inventors: Christopher M. Scanlan, Timothy L. Olson
-
Publication number: 20130241074Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.Type: ApplicationFiled: May 10, 2013Publication date: September 19, 2013Applicant: DECA Technologies Inc.Inventors: Christopher M. Scanlan, Timothy L. Olson
-
Publication number: 20130244376Abstract: A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap.Type: ApplicationFiled: May 9, 2013Publication date: September 19, 2013Applicant: DECA Technologies Inc.Inventor: Christopher M. Scanlan
-
Patent number: 8535978Abstract: A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer.Type: GrantFiled: September 30, 2012Date of Patent: September 17, 2013Assignee: Deca Technologies Inc.Inventor: Christopher M. Scanlan
-
Publication number: 20130168874Abstract: A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer.Type: ApplicationFiled: September 30, 2012Publication date: July 4, 2013Applicant: DECA TECHNOLOGIES INC.Inventor: Deca Technologies Inc.
-
Publication number: 20130168849Abstract: A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap.Type: ApplicationFiled: December 30, 2011Publication date: July 4, 2013Applicant: DECA TECHNOLOGIES, INC.Inventor: Christopher M. Scanlan
-
Publication number: 20130167102Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.Type: ApplicationFiled: February 25, 2013Publication date: June 27, 2013Applicant: DECA TECHNOLOGIES INCInventor: DECA Technologies Inc.
-
Publication number: 20110202896Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.Type: ApplicationFiled: September 7, 2010Publication date: August 18, 2011Applicant: DECA TECHNOLOGIES INC.Inventors: Christopher M. Scanlan, Timothy L. Olson
-
Publication number: 20110198762Abstract: A method of panelized packaging is described in which a plurality of die units are placed on a dielectric film. The dielectric film is then cured to lock the plurality of die units in place, which are then encapsulated. The cured dielectric film is then patterned utilizing a mask-less patterning technique.Type: ApplicationFiled: January 5, 2011Publication date: August 18, 2011Applicant: DECA TECHNOLOGIES INC.Inventor: Christopher M. Scanlan