Abstract: An operating method for a neural processing unit is provided. The method includes determining, by a controller, that an operation performed in a first convolution layer is a transpose convolution operation, dividing, by the controller, a kernel used for the transpose convolution operation into a plurality of sub-kernels, and performing, by at least one processing element, a convolution operation between an input feature map and each of the plurality of sub-kernels in the first convolution layer.

Abstract: A neural network processing unit (NPU) includes a processing element array, an NPU memory system configured to store at least a portion of data of an artificial neural network model processed in the processing element array, and an NPU scheduler configured to control the processing element array and the NPU memory system based on artificial neural network model structure data or artificial neural network data locality information.

Abstract: A neural processing unit includes a controller to receive a compiled machine code of an artificial neural network (ANN) model for predicting cardiovascular disease, the ANN model configured to receive sensing data of ECG, respiration, pulse rate, acceleration, and/or body temperature and to output a probability of disease onset for cerebral infarction, heart failure, and/or ischemic heart disease in a user; an input circuit configured to receive a plurality of input signals corresponding to the ANN model; a processing element (PE) array to perform a calculation of the ANN model; a special function unit (SFU) to perform a special function of calculating the ANN model; and an on-chip memory to store operation data of the ANN model, wherein the controller controls the PE array, the SFU, and the on-chip memory to process the ANN model according to data locality information of the ANN model included in the compiled machine code.

Abstract: A system for an artificial neural network (ANN) includes a main memory including a dynamic memory cell electrically coupled to a bit line and a word line; and a memory controller configured to selectively omit a restore operation during a read operation of the dynamic memory cell. The main memory may be configured to selectively omit the restoration operation during the read operation of the dynamic memory cell by controlling a voltage applied to the word line. The memory controller may be further configured to determine whether to perform the restoration operation by determining whether data stored in the dynamic memory cell is reused. Thus, the system optimizes an ANN operation of the processor by utilizing the ANN data locality of the ANN model, which operates at a processor-memory level.

Abstract: A neural processing unit is provided. The neural processing unit may include a plurality of processing elements configured to perform bilinear interpolation to generate second data by expanding resolution of first data. The first data may include first pixel data, and the second data may include second pixel data. The plurality of processing elements may include at least one processing element configured to receive the first pixel data and a weight for performing the bilinear interpolation and to calculate the second pixel data. The plurality of processing elements may be configured as a processing element array that may include at least one delay buffer.

Abstract: A neural processing unit may comprise a first circuitry including a plurality of processing elements (PEs) configured to perform operations of an artificial neural network model, the plurality of PEs including an adder, a multiplier, and an accumulator, and a clock signal supply circuitry configured to output one or more clock signals. When the plurality of PEs include a first group of PEs and a second group of PEs, a first clock signal among the one or more clock signals, may be supplied to the first group of PEs and a second clock signal among the one or more clock signals, may be supplied to the second group of PEs. At least one of the first and second clock signals may have a preset phase based on a phase of an original clock signal.

Abstract: A system-on-chip (SoC) may comprise a semiconductor substrate; a first circuitry, disposed on the semiconductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model; a second circuitry, disposed on the semiconductor substrate, provided for a second NPU configured to perform operations of an ANN model; and a third circuitry, disposed on the semiconductor substrate, configured to generate a control signal to selectively output one or more clock signals, wherein each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs may include an adder, a multiplier, and an accumulator, and wherein the one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal.

Abstract: A neural processing unit includes an internal memory including a plurality of memory units; a controller configured to control read and write operations of data in at least one of an input feature map domain, a weight domain, and an output feature map domain with respect to each of the plurality of memory units based on an operation schedule in a machine code in which a plurality of operation steps of an artificial neural network model are set.

Abstract: An electronic device mounted on a fixed or a movable apparatusapparatus is provided. The electronic device may comprise an image signal processor (ISP) for at least one camera; a neural processing unit (NPU), including a plurality of processing elements (PEs), configured to: process an operation of an artificial neural network model trained to detect or track at least one object, based on an input feature map generated from at least one image, which is acquired via the ISP from the at least one camera, and output an inference result; and a signal generator generating a signal applicable to the at least one camera or the ISP.

Abstract: An image processing method includes receiving an image including an object; classifying at least one object in the image using a first model on the basis of an artificial neural network configured to classify the at least one object by inputting the image; and obtaining an image having improved quality according to the at least one object by inputting the image in which the at least one object is classified by using at least one model among a plurality of second models on the basis of an artificial neural network configured to output a specialized processing applied image according to a particular object by inputting the received image.

Abstract: A control method of an image signal processor for an artificial neural network may be configured to include a step of acquiring an image, a step of determining at least one image characteristic data corresponding to the image, and a step of determining an image correction parameter (SFR preset) for improving an inference accuracy of an artificial neural network model based on the at least one of image characteristic data and an inference accuracy profile of an artificial neural network model.

Abstract: An electronic device mounted on a fixed or a movable apparatus is provided. The electronic device may comprise a neural processing unit (NPU), including a plurality of processing elements (PEs), configured to process an operation of an artificial neural network model trained to detect or track at least one object and output an inference result based on at least one image acquired from at least one camera; and a signal generator generating a signal applicable to the at least one camera.

Abstract: A system for an artificial neural network (ANN) includes a processor configured to output a memory control signal including an ANN data locality; a main memory in which data of an ANN model corresponding to the ANN data locality is stored; and a memory controller configured to receive the memory control signal from the processor and to control the main memory based on the memory control signal. The memory controller may be further configured to control, based on the memory control signal, a read or write operation of data of the main memory required for operation of the artificial neural network. Thus, the system optimizes an ANN operation of the processor by utilizing the ANN data locality of the ANN model, which operates at a processor-memory level.

Abstract: A method of programming an activation function is provided. The method includes generating a segment data for segmenting the activation function; segmenting the activation function into a plurality of segments using the segment data; and approximating at least one segment of the plurality of segments to a programmable segment.

Abstract: A neural processing unit (NPU) for decoding video or feature map is provided. The NPU may comprise at least one processing element (PE) to perform an inference using an artificial neural network. The at least one PE may be configured to receive and decode data included in a bitstream. The data included in the bitstream may comprise data of a base layer. Alternatively, the data included in the bitstream may comprise data of the base layer and data of at least one enhancement layer. The data of the base layer included in the bitstream may include a first feature map. The data of the at least one enhancement layer included in the bitstream may include a second feature map.

Abstract: A system may comprise a neural processing unit (NPU) including at least one memory and a plurality of processing elements (PEs) capable of performing operations for at least one artificial neural network (ANN) model. The plurality of PEs may include an adder, a multiplier, and an accumulator. The plurality of PEs may include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal.

Abstract: A neural processing unit includes an internal memory including a plurality of memory units; a controller configured to control read and write operations of data in at least one of an input feature map domain, a weight domain, and an output feature map domain with respect to each of the plurality of memory units based on an operation schedule in a machine code in which a plurality of operation steps of an artificial neural network model are set.

Abstract: A neural processing unit of a binarized neural network (BNN) as a hardware accelerator is provided, for the purpose of reducing hardware resource demand and electricity consumption while maintaining acceptable output precision. The neural processing unit may include: a first block configured to perform convolution by using a binarized feature map with a binarized weight; and a second block configured to perform batch-normalization on an output of the first block. A register having a particular size may be disposed between the first block and the second block. Each of the first block and the second block may include one or more processing engines. The one or more processing engines may be connected in a form of pipeline.

Abstract: A method for programming an activation function is provided. The method includes generating segment data for segmenting the activation function; segmenting the activation function into a plurality of segments using the segment data; and approximating at least one segment of the plurality of segments as a programmable segment. An apparatus for performing the method may include a programmable activation function generator configured to generate segment data for segmenting an activation function; segment the activation function into a plurality of segments using the generated segment data; and approximate at least one segment of the plurality of segments as a programmable segment. By using segment data, various non-linear activation functions, particularly newly proposed or known activation functions with some modifications, can be programmed to be processable in hardware.

Abstract: A neural processing unit (NPU) and a method of operating the same are provided. The NPU may include an artificial intelligence (AI) calculation unit configured to process artificial neural network calculation of at least one artificial neural network model; and an internal memory including at least one memory unit configured to store data of at least one domain among first to third domain data of the at least one artificial neural network model. The at least one memory unit may include a plurality of sub-memory units configured to perform time-division operation. A bandwidth of the at least one memory unit is based on a number of the plurality of sub-memory units.