Abstract: A memory efficient time de-interleave, de-puncture and viterbi decoder circuit is provided for decoding frames of digital data that is time interleaved over a plurality of data frames, wherein the time interleaved digital data includes convolutionally encoded data. The circuit includes a time de-interleave block having an input receiving a stream of the digital data and an output connected to an input of a de-puncture block, which has an output connected to an input of a viterbi decoder block. The time de-interleave block is adapted for communication with an external memory wherein the time de-interleave block establishes a plurality of address pointers thereto corresponding to the plurality of time interleaved data frames. In accordance with the address pointers, the time de-interleave circuit stores the viterbi metric data for a number of data frames within the external memory in a storage efficient manner.

Abstract: A lead-free solder alloy suitable for forming solder joints of a surface-mount integrated circuit device, such as a flip chip. The solder alloy has a sufficiently low liquidus temperature to achieve desirable reflow properties at temperatures of 240.degree. C. and less, and is therefore compatible with integrated circuit processes. The solder alloy has a sufficiently high solidus temperature to ensure that solder joints formed with the alloy exhibit suitable mechanical properties at application temperatures up to 150.degree. C. when mounting a component to a laminate substrate. The solder alloy generally contains, in weight percent, about 7 to about 11% indium, about 2.5 to about 3.5% silver, and about 0.5 to about 1.5% copper, the balance tin and incidental impurities.

Abstract: In an automotive radio system an amplifier is capable of detecting speaker faults. A fault signal from the amplifier is received by a microprocessor which sends a fault message to a radio display and/or stores fault data which can be accessed via a serial data link by a diagnostic tool. One embodiment of the amplifier has an output pin for outputting distortion signal, and that pin is used when distortion is not likely to also output a fault signal which reveals the presence of a fault. Another embodiment of the amplifier has a data storage register which receives data on the type of fault and the affected channel, and a data bus to send the data to the microprocessor.

Abstract: An IC driver mounted on a LCD display package contains a sensor for determining temperature of the LCD cell, and a digital value of the temperature is serially transmitted to a remote microprocessor which determines compensated voltage and sends voltage command data back to the IC driver which produces a drive voltage by a charge pump. A digital code on the LCD cell identifies cell response characteristics and the code is used by the microprocessor to calculate the desired voltage. A ROM in the IC driver stores many bit-mapped images which are selected by the microprocessor for display.

Abstract: A technique for reducing FM intrusion in an AM section of an AM/FM receiver. In one embodiment, a first switch is provided between an FM tuner filter circuit and an AM tuner circuit. A second switch is provided between the FM tuner circuit and a reference potential. When the receiver is in an FM mode, the first switch is closed so that a tuning voltage can be applied to the FM tuner circuit, and the second switch is open to prevent the tuning voltage from being affected by the reference potential. When the receiver is switched to the AM mode, the first switch is open to prevent intermodulation product signals generated by the FM tuner circuit from reaching the AM tuner circuit, and the second switch is closed to connect the FM tuner circuit to the reference potential. By connecting the FM tuner circuit to the reference potential when the receiver is in the AM mode, the tuning of the FM tuner circuit is shifted out of the FM bandwidth, thus eliminating intermodulation products at the AM frequencies.

Abstract: An audio amplifier having an improved bi-polar transistor variable impedance circuit which is inexpensive to implement and which exhibits improved linearity. The resistance characteristic of the circuit is linearized with respect to the input signal strength through the addition of a diode between the control voltage and the base of the bi-polar transistor. This simple and inexpensive combination significantly improves the resistance linearity, allowing the transistor to handle significantly higher input signal voltages without increasing the output signal distortion. Additionally, the linearity of the control voltage response is improved through the addition of a second transistor-diode combination connected in current-mirroring relationship to the variable impedance transistor-diode combination. This circuit is particularly useful in applications requiring a wide-range open-loop control, such as a volume or tone control.

Abstract: An all-silicon monolithic capacitive absolute pressure-sensing device and method for making the same. The device employs a single-crystal silicon diaphragm that serves at a flexible capacitor plate of a variable capacitor. The diaphragm is bonded to a single-crystal silicon wafer to overlie a cavity etched into the wafer. A fixed capacitor plate of the variable capacitor is formed by a heavily-doped region at the bottom of the cavity. A thin dielectric layer is grown on the fixed capacitor plate to complete the capacitor. The cavity has a minimal depth such that the fixed capacitor plate provides overpressure protection for the diaphragm. At least a portion of the operating range of the pressure sensor occurs while the diaphragm is contacting the doped region. As a result, the capacitive output signal of the pressure sensor is produced by changes in contact area between the diaphragm and a thin dielectric situated on the doped region in response to pressure applied to the diaphragm.

Abstract: A transient suppressor comprises a self-triggered silicon control rectifier (SCR) that forms a drive circuit for an NPN power transistor. The SCR and the NPN power transistor are combined, along with other elements, into an integrated circuit (IC) by a junction isolated BiCMOS process. The SCR self-triggers upon being subjected to an inductive flyback condition created by an inductive load and renders the NPN transistor conductive, thereby allowing the NPN power transistor, having a relatively large semiconductor region, to effectively snub the current created by the negative feedback condition. The transient suppressor may be used in either a high-side or low-side driver arrangement and the SCR/NPN power transistor combination may further be combined with load driving and other circuitry on a single integrated circuit.

Abstract: A media-compatible sensing structure (210) that employs strain-sensing elements (222) formed in or on a silicon chip (212). The sensor (210) generally includes a metal body (214) having a diaphragm (216) and an edge (226) formed by an abrupt change in the thickness of the metal body (214) in a direction normal to the diaphragm (216). The silicon chip (212) is secured directly to the metal diaphragm (216) and has at least one strain-sensing element (222) aligned with the edge (226) of the body (214) in the direction normal to the diaphragm (216), such that movement of the diaphragm (216) induces strain in the silicon chip (212) that is localized at the strain-sensing element (222).

Abstract: A process for depositing an encapsulating material (16) on and around a COB die (10) and other wire-bonded device, without producing voids that encourage premature fatigue fracturing of the material (16) and wires (14) that electrically connect the device (10) to a circuit board (12). The process generally entails mounting and wire bonding a die (10) to a circuit board (12) with multiple bond wires (14). The encapsulation material (16) is then deposited along a first edge (18) of the die, and sequentially along the remaining edges (20, 22, 24) of the die (10), each successive edge being contiguous with the preceding edge, until the entire perimeter of the die (10) is surrounded and contacted with the material (16). The encapsulation material (16) encapsulates only those portions of the wires (14) immediately adjacent the die (10), with the remainder of the wires (14) remaining exposed.

Abstract: A method of making an EPROM transistor in a high density CMOS integrated circuit having a gate electrode to metallization capacitor. The EPROM transistor is made using only the steps used to make the other components of the high density CMOS integrated circuit. The EPROM transistor is programmable at low voltages which high density CMOS transistors can handle.

Abstract: A semiconductor device that uses polysilicon as an electrostatic bonding medium and as a lead transfer for multiple lead connection to one or more electrical devices within a vacuum sealed chamber. A semiconductor region, such as a heavily built P++ silicon region, is bonded to a glass substrate of the device. The semiconductor region includes a recess that defines a chamber between the semiconductor region and the substrate. Multiple internal electrodes or lead transfers within the chamber pass through separate electrical connection regions in a polysilicon sealing layer that seals the semiconductor region to the substrate. In one embodiment, each of the separate electrical connection regions includes an upper polysilicon region and a lower polysilicon region separated by a dielectric layer. The lower polysilicon region includes a first separate polysilicon region electrically connected to one of the internal leads and a second separate polysilicon region electrically connected to an external lead.

Abstract: An improved current monitor for measuring current over a wide dynamic range. The current monitor includes a low current channel, a high current channel, and a switch for selecting the low current channel if the measured current is below a predetermined level and the high current channel if the current is above the predetermined level. The output of the high current channel is voltage encoded by adding a fixed offset. The current monitor determines that the measured current is from the low current channel if the reading is below the offset and from the high current channel if the reading is above the offset. A current level output device automatically outputs a decoded current reading based on this determination. The current monitor also incorporates a low current error compensation circuit to compensate for parasitic current when the current monitor is using the high current channel.

Abstract: A method for determining the actual frequency of an inaccurate clock signal then using the actual frequency to generate a compensation factor to correct calculations using the clock signal. The method includes counting the number of clock pulses in the clock signal over a predetermined and programmable period of time, and based on the clock pulse count, determining the actual frequency of the clock signal. Once the actual frequency of the clock signal is determined, this value is used to generate the compensation factor based on the expected or rated frequency of the clock signal to compensate for the calculations using the clock signal. The method has a particular application for use in a powertrain control module incorporating a low frequency resonator and a high frequency system clock, where the resonator generates an inaccurate clock signal which is highly stable for short periods of time and the system clock is relatively stable over long term but suffers from short term jitter.

Abstract: A multi-chip module that incorporates multiple flip chip (16) mounted on a daughter board (12), which in turn is flip-chip mounted onto a product mother board (10). The daughter board (12) is preferably a silicon substrate having solder bump terminals (14) and at least one conductor pattern on a surface thereof. The surface of the daughter board (12) may also have conductive runners and any passive electronic components required by the module. Mounted to the conductor pattern of the daughter board (12) are the flip chips (16) having solder bump terminals (18) that are registered and soldered to the conductor pattern of the daughter board (12). The solder bump terminals (14) of the daughter board (12) are then registered and soldered to a complementary conductor pattern on the mother board (10), such that the flip chips (16) are disposed between the daughter board (12) and the mother board (10).

Abstract: A silicon sensing cell (12) capable of sensing force and/or displacement, and particular embodiments of the sensing cell (12) for particular force and/or displacement-sensing applications. The sensing cell (12) generally includes a diaphragm (18), a silicon sensing element (28) operatively associated with the diaphragm (18) to sense strain or deflection of the diaphragm (18), a base (14) supporting the diaphragm (18) so that the base (14) and the diaphragm (18) define a recess (22), and a force-distributing member (20) within the recess (22) and contacting the diaphragm (18). The diaphragm (18) is preferably single-crystal silicon, and the sensing element (28) can be a piezoresistive, piezoelectric or capacitive element preferably formed in the diaphragm (18) using semiconductor fabrication processes.

Abstract: A transparent pointer has a rear surface coated with white paint and the remainder is covered by a highly reflective metal layer except for a light emitting indicator strip and a light receiving surface. Stationary high flux LEDs mounted behind the pointer illuminate the light receiving surface. Received light is efficiently reflected to the indicator strip to produce a bright line suitable for viewing through a dark face plate to achieve a dark dead front appearance. To avoid reflections from the pointer the reflective layer is covered with a black film.

Abstract: An improved method of manufacturing multi-layer thick film circuits that effectively eliminates the trade-off between thickness and definition, permitting dielectric layers of increased thickness with no pin-holes, and at the same time, more precise definition of dielectric features, such as via openings and solder stops. The dielectric features are precisely defined by an initial thin layer of dielectric material, referred to as a feature definition print, or FDP. After the FDP has been dried but not yet fired, a via can be formed by printing a comparatively thick cover layer of dielectric, over-lapping the edges of the FDP. Due to the porous nature of the dried but not fired FDP, it absorbs solvent from the dielectric cover layer, which inhibits the spreading of the dielectric cover layer. The FDP is then co-fired with the first dielectric layer, and a second dielectric layer may be provided atop the fired first layer to further increase the overall dielectric thickness, if so desired.

Abstract: A CMOS analog divider/multiplier/ratiometry circuit that provides a ratiometric output of two or more inputs, where the output is insensitive to process parameters and temperature variations effecting the circuit. The analog divider/multiplier/ratiometry circuit includes a multiplier portion made up of six FET devices. The six FET devices are electrically connected together so that first and second current outputs from the multiplier portion are insensitive to process parameter and temperature variations effecting the circuit. A first input current is applied to a gate terminal of one of the FET devices and a second input current is applied to a gate terminal of the FET devices in the multiplier portion of the circuit. The first and second input currents are based on currents generated by first and second linear voltage-to-current converter input circuits that are responsive to first and second input voltage, respectively, whose ratio or product is to be determined at the output of the circuit.

Abstract: An electrical input buffer circuit is provided for receiving an input signal such as an electronic spark timing signal and providing an output signal despite the presence of noise. The input buffer circuit receives a control signal and a reference voltage signal, and the voltage potential therebetween provides a differential input. A voltage divider network is coupled between the inputs for producing a first voltage potential and a second voltage potential in response to the differential input. A differential pair of NPN type transistors compares the control signal to a threshold value. The input buffer circuit produces an output high or low signal as a function of the input control voltage and is allowed to operate above and below local ground.