Abstract: A digital computer chassis has a front and rear wall with a strut fastened to both the front and rear walls, positioned to strengthen the chassis. A power supply and a hard disk drive are located within the chassis and connected to and supported by the strut. The power cable from the power supply is positioned within a channel formed in the strut, terminating in an on/off switch. The power cable is shielded from the electrical components within the chassis by the strut. With the surrounding cover in place, a monitor may be placed on the cover, supported by the strut.
Abstract: A shipping container for an article includes a floor on which the article is placed, the top surface of which is elevated from the supporting surface upon which the container rests, by a fixed dimension. Four side structures surround the floor and a top panel contacts the side structures to form an enclosure for the article. One of the side structures has at least one flap that, when opened, permits a ramp, that is part of the side structure, in the form of an inclined plane, to be pivoted into position against the floor. The height of the inclined plane approximates the fixed dimension so that the article can be moved horizontally within the container and then down the ramp for removal. Reinstallation of the article into the container requires moving the article up the inclined plane, onto the floor of the container.
Abstract: An electronic circuit for the detection of required operational speed of one or more integrated circuit semiconductor chips is used in conjunction with an off-the-shelf integrated circuit tester. The tester provides timing, control and a display. Each of the integrated circuit semiconductor chips is provided with a ring oscillator circuit for generating a series of pulses, timed by the tester for a fixed period of time. A counter, formed in each of the semiconductor chips counts the number of pulses generated during the fixed period of time. A number, generated in the tester, indicative of a required speed of operation is set in a latch assembly that is formed in each of the semiconductor chips. A comparator, also formed in each of the semiconductor chips, compares the contents of the latch with the contents of the counter and if the contents of the counter is equal to or larger than the contents of the latch, the tested semiconductor chip is acceptable. A display in the tester indicates the result.
Abstract: A computer system includes a first processor, a second processor, a bus shared by the first processor and the second processor, and a power on reset coordination means for the first processor and the second processor. The power on reset coordination means includes means for resetting the first processor and the second processor, and means for deasserting reset to the first processor and second processor sequentially. It should be noted that in embodiments of the present invention, some "other" processor must be "up" in order to reset the "first" processor or to deassert reset to it.
May 25, 1990
Date of Patent:
December 3, 1991
Dell USA Corporation
Thomas H. Holman, Jr., David R. Lunsford
Abstract: A digital computer system has an I/O command recovery circuit for providing suitable I/O recovery time for any one of a plurality of associated peripheral devices. The circuit, transparent to both software and system execution speed, enables the digital computer system to efficiently run certain software application programs that interface with the peripheral devices and provide timing loops for setting the command recovery time. Those certain software application programs, designed for earlier and slower computer systems, run the timing loops in too short a time to provide the maximum I/O recovery time. The addition of the I/O command recovery circuit provides selectable and suitable recovery times for each of the associated peripheral devices, including no recovery time for those devices not requiring it.
Abstract: A digital computer system having a local cache memory and a system bus also has a subsystem for regulating the effective processing rate of the central processor unit (CPU) of the computer system. A programmable counter/timer is programmed by data from the CPU to provide a periodic pulse of desired periodicity and pulse width for entry into a bus controller. The bus controller arbitrates use of the system bus, sending a request signal to the CPU requesting the CPU to relinquish use of the bus and it receives an acknowledgement signal from the CPU indicating its relinquishment of use of the bus. The local cache memory is flushed through the cache controller to prevent the CPU from using the local cache memory. This causes the CPU to be periodically active when using the system bus and periodically inactive when the system bus is relinquished, thereby establishing the effective processing rate of the CPU as set by the programmable counter/timer.
Abstract: A personal computer system has an I/O channel and a memory channel with a main logic board incorporating both the I/O channel and the memory channel. The computer has eight (8) expansion slots including a dual-purpose expansion slot for providing space for selective connections of I/O devices through the use of full-length logic cards or half-length logic cards being inserted into edge connectors, High speed memory, including memory control, is mounted on the main logic board and expansion memory, controlled by the memory control is mounted on a printed circuit card that is connected to the memory channel in position within the dual-purpose expansion slot, occupying approximately one-half of that slot, thereby enabling the dual-purpose expansion slot to encompass both the expansion memory and a half-length logic card. In another embodiment, the half-length logic card and the memory card within the dual-purpose expansion slot are integrated into a single logic/memory card.