Abstract: A method for using a single spare block pool in flash memory comprising: allocating a plurality of flash memory arrays, wherein each flash memory array comprises a plurality of flash memory blocks; within a main flash memory array: allocating a used block pool comprising a plurality of used blocks and allocating a main spare block pool comprising a plurality of spare blocks; within each of the other flash memory arrays: allocating a used block pool comprising multiple used blocks; allocating a minimum spare block pool comprising a minimum number of spare blocks; allocating the main spare block pool and each of the minimum spare block pools to a single spare block pool; transferring a spare block from the main spare block pool to one of the minimum spare block pools; and transferring a spare block from a first minimum spare block pool to a second minimum spare block pool.

Abstract: A flash memory controller, a non-transitory computer readable medium and a method for performing operations with a flash memory device, the method may include receiving, by a flash memory controller, a request to perform a requested operation with the flash memory device; selecting multiple selected instructions to be executed by a programmable module of the flash memory controller, based upon (a) an interface specification supported by the flash memory device and (b) the requested operation; wherein the programmable module comprising multiple operation phase circuits; and executing the multiple selected instructions by the programmable module, wherein the executing of the multiple selected instructions comprises executing a plurality of selected instructions by multiple operation phase circuits; wherein different operation phase circuits are arranged to execute different operation phases of the requested operation.

Abstract: A system, a method and a non-transitory computer readable medium for generating soft information. The method may include performing a first set of read attempts of flash memory cells using a first set of read thresholds to provide first read results; calculating for each flash memory cell in response to the first read results, first cell information indicative of a first change-inducing read threshold; performing a second set of read attempts of the flash memory cells using a second set of read thresholds to provide second read results, calculating for each flash memory cell in response to the second read results, second cell information indicative of a second change-inducing read threshold; and generating, for each flash memory cell soft information in response to the first cell information and the second cell information of the flash memory cell.

Abstract: A computer readable medium, a system and a method for flash memory device parameter optimization, the method may include: receiving or generating an estimate of a wear level of at least one group of flash memory cells of the flash memory device, and finding erase parameters and programming parameters to be applied on one or more groups of flash memory cells of the flash memory device in response to estimate of the wear level.

Abstract: A method, a computer readable medium and a system for managing flash memory. The method may include receiving multiple data sectors from an interface; writing the multiple data sectors into a data buffer that is nonvolatile; creating a pointer in a data management structure that is stored in a metadata buffer that is nonvolatile, for each data sector corresponding to a storage location of the data sector in the data buffer; if a predefined condition is reached, merging data sectors stored in the data buffer with data sectors that are already stored in a sequential nonvolatile portion of the flash memory device, wherein the sequential nonvolatile portion differs from the data buffer.

Abstract: A flash memory controller, a computer readable medium and a method. The method may include performing, by a flash memory controller, multiple read attempts of a group of flash memory cells, using multiple read thresholds, to provide multiple read results; determining, by the flash memory controller and based upon the multiple read results, a reliability metric of each of the multiple read results; and error correction decoding the multiple read results based upon reliability metrics associated with the multiple read results.

Abstract: A system and method for unbiased rounding away from, or toward, zero by truncating N bits from a M bit input number to provide a M?N bit number, and adding the equivalent value of ‘½’ to the M?N bit number unless the input number is negative, or positive, respectively, and the N truncated bits represent exactly ½. The method for rounding away from zero may include outputting a (M?N) bit truncated number if the M-bit input number is negative and the sequence of N truncated bits comprises a most significant bit of 1, followed by zeros; and otherwise, computing and outputting a sum of (a) a number that has an equivalent value of one followed by (N?1) replicas of zero, the one provided by applying a logical operation on the most significant bit of the sequence of truncated bits and (b) the (M?N) bit truncated number.

Abstract: A system and method for reading memory cells in a multi-level cell memory device. A set of thresholds may be received for reading a current page of the memory cells. The set of threshold may include hard decision thresholds for hard decoding, soft decision thresholds for soft decoding, erase thresholds for erase decoding and/or other combinations of thresholds. The set of thresholds may be divided into a plurality of groups of thresholds. The current page may be simultaneously read using multiple thresholds, where each of the multiple thresholds is divided into a different group of thresholds.

Abstract: A non-transitory computer readable medium, a flash controller and a method for state responsive encoding and programming; the method may include encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells; and programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state, the state being either an estimated state or an actual state.

Abstract: A flash memory controller, a non-transitory computer readable medium and a method for reading flash memory cells of a flash memory module. The method may include calculating a group of read thresholds to be applied during a reading operation of a set of flash memory cells that belong to a certain row of the flash memory module based upon a compressed representation of reference read thresholds associated with multiple reference rows of the flash memory module; and reading the set of flash memory cells by applying the group of reference read thresholds to provide read results.

Abstract: A system, computer readable program, and method for programming flash memory, the method includes: providing multiple pairs of most significant bit (MSB) page uncoded bit error rates (UBERs) and least significant bit (LSB) page UBERs; selecting a selected MSB page code rate and a selected LSB page code rate so that a selected MSB page UBER associated with the selected MSB page code rate and a selected LSB page UBER associated with the selected LSB page code rate support a highest average UBER out of the multiple pairs of MSB page UBERs and LSB page UBERs, wherein the selected MSB page code rate and the selected LSB page code rate are obtainable under a desired code rate constraint; and determining an encoding and programming scheme that may be based on the selected MSB page UBER, the selected MSB code rate, the selected LSB page UBER and the selected LSB code rate.

Abstract: A decoder, an encoder, a decoding method and an encoding method are provided. The encoding method includes receiving data; generating a set of first codewords by applying a first encoding process on the received data; and performing a second encoding process on a folded version of each first codeword to provide a set of second codewords, wherein a folded version of a first codeword is representative of a storage of the first codeword in a two dimensional memory space, wherein the second codeword comprises redundancy bits.

Abstract: A system, a method and a non-transitory computer readable medium are disclosed. The non-transitory computer readable medium may store instructions for: (I) interleaving at least two portions of a first codeword of a group of codewords between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule; and (II) interleaving different portions of other codewords of the group of codewords between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule. The at least two portions may be programmed to rows in different flash memory blocks, and the flash memory planes may belong to the same or multiple flash memory dies. The programming type ordering may define different decoupling sequence steps with sizes set for different programming types according to sensitivity to noise.

Abstract: A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values.

Abstract: A flash memory apparatus that may include a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain memory portions; allocate data, during said first duration of time, only to said certain memory portions, thereby to define a retired memory portion for said first duration of time; determine to copy data from a certain memory portion to a retired memory portion based upon a relationship between effective cycle counts of the certain memory portion and the retired memory portion, an effective cycle count of any memory portion is responsive to a number of erase-write cycles and to an effective duration of time the memory portion had available to recover from erase-write cycles; and copy the data from the certain memory portion to the retired memory portion.

Abstract: A flash memory controller, a computer readable medium and a method for writing to a flash memory device, the method may include receiving multiple logical pages, each logical page having a logical address; determining to write a logical page into a selected physical page of the flash memory device; calculating a hash value for each logical page of the multiple logical pages in response to (a) a logical address of the logical page and (b) a physical page index, to provide multiple hash values of the multiple logical pages.

Abstract: A method for accessing a flash memory, the method includes: receiving a read request that is associated with a logical address that is mapped to a physical address of a set of flash memory cells; accessing multiple mapping data structures of different granularity to obtain the physical address of the set of flash memory cells; wherein during at least one point in time at least one mapping data structure is stored in an erase block and wherein the erase block comprises multiple physical pages that are written in a sequential manner and are associated with logical page addresses that are assigned in a random manner; and reading a content of the set of flash memory cells.

Abstract: A method for programming data into a first plurality of rows within a second plurality of erase sectors of a flash memory device using a programming process having at least one selectable parameter, the method includes characterizing each of at least one row subsets, each row subset comprising at least one row from among said first plurality of rows, thereby to generate at least one row subset characteristic value; and programming data into at least a portion of at least one individual row belonging to at least one row subset, using a programming process having at least one selectable parameter, said at least one selectable parameter being set at least partly in accordance with the row subset characteristic value characterizing a row subset to which said individual row belongs; wherein at least two row subsets of an array of flash memory cells differ from each other by their row subset characteristic values.

Abstract: Apparatus and methods for operating a flash device characterized by use of Lee distance based codes in a flash device so as to increase the number of errors that can be corrected for a given number of redundancy cells, compared with Hamming distance based codes.

Abstract: A system that includes a multiplicity of flash memory cells; a reading apparatus; a writing apparatus for writing logical data from temporary memory into individual flash memory cells from among said multiplicity of flash memory cells, thereby to generate a physical representation of the logical data including a plurality of physical levels at least some of which represent, to said reading apparatus, at least one bit-worth of said logical data; and a special cell marking apparatus operative to store an earmark in at least an individual one of said multiplicity of flash memory cells for subsequent special treatment.