Patents Assigned to Deog-Kyoon Jeong
  • High speed serial link for fully duplexed data communication
    Patent number: 5802103
    Abstract: A system for converting between parallel data and serial data is described. In the system 10, individual bits of the parallel data 12 are latched into individual registers 117. Each register 117 is coupled to a corresponding AND gate 110 which is also connected to receive phased clock signals. The output terminals of the AND gates 110 are connected to an OR gate 115. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: September 1, 1998
    Assignees: Sun Microsystems, Inc., Deog-Kyoon Jeong
    Inventor: Deog-Kyoon Jeong
  • High speed serial link for fully duplexed data communication
    Patent number: 5714904
    Abstract: A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is converted into serial data.
    Type: Grant
    Filed: June 6, 1994
    Date of Patent: February 3, 1998
    Assignees: Sun Microsystems, Inc., Deog-Kyoon Jeong
    Inventor: Deog-Kyoon Jeong
  • Sysem for distributing clock signals
    Patent number: 5712585
    Abstract: A system for convening between parallel data and serial data is described. In the system (b 10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is convened into serial data.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: January 27, 1998
    Assignees: Deog-Kyoon Jeong, Sun Microsystems
    Inventor: Deog-Kyoon Jeong
  • High speed serial link for fully duplexed data communication
    Patent number: 5675584
    Abstract: A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is converted into serial data.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: October 7, 1997
    Assignees: Sun Microsystems, Inc., Deog-Kyoon Jeong
    Inventor: Deog-Kyoon Jeong
  • High speed serial link for fully duplexed data communication
    Patent number: 5587709
    Abstract: A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is converted into serial data.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: December 24, 1996
    Assignees: Deog-Kyoon Jeong, Sun Microsystems, Inc.
    Inventor: Deog-Kyoon Jeong