Abstract: A brightness compensation method includes steps of: determining a start time of a backlight compensation drive signal of a current frame according to an end time of a standard backlight drive signal of the current frame, and starting transmitting the backlight compensation drive signal to a backlight assembly at the start time of the backlight compensation drive signal; and determining an end time of the backlight compensation drive signal according to a time length of the front porch period of the current frame, and stopping transmitting the backlight compensation drive signal to the backlight assembly at the end time of the backlight compensation drive signal, wherein, the backlight assembly emits light as standard backlight according to the standard backlight drive signal when receiving the standard backlight drive signal, and emits light as compensated backlight according to the backlight compensation drive signal when receiving the backlight compensation drive signal.

Abstract: The present application discloses a display control method, a display control apparatus, a control apparatus and a display device. The display control method comprises: frequency multiplying or dividing an input display signal to generate an output display signal based on the relationship between the field frequency of the input display signal and the maximum field frequency supported by a display apparatus, the field frequency of the output display signal being not less than the minimum field frequency supported by the display apparatus and not greater than the maximum field frequency supported by the display apparatus; and controlling a backlight module to be turned on based on the field frequency of the output display signal, so that the liquid crystal stabilization time is increased. With the present application, the motion blur reduction effect can be improved, the blurred moving pictures can be reduced, and the smearing can be reduced.

Abstract: A pulse width clock topology structure circuit, comprising a clock pulse width generation module and a clock topology delay module. The clock pulse width generation module connects an input clock and n stages of delay sub-modules in series; an output end of each stage of delay sub-module is connected to an input end of a selector; a certain required delay clock is selected by means of m+1 control signals of the selector, and an “AND” operation is performed on the required delay clock and an original input clock to generate different pulse width clock outputs as inputs of the clock topology delay module; and the clock topology delay module can generate a plurality of different delay clocks for different latches to use.

Abstract: The present application discloses a method and a device for eliminating a brightness mura defect of a liquid crystal display, and relates to the technical field of liquid crystal displays. The method disclosed by the present application includes the following steps: acquiring an image to be displayed, wherein the image to be displayed includes a plurality of pixels; determining a compensation coefficient corresponding to each channel of each of the pixels according to an original gray scale value corresponding to each channel of each of the pixels; calculating a compensation gray scale value corresponding to each channel of each of the pixels according to the original gray scale value and the compensation coefficient corresponding to each channel of each of the pixels; and outputting and displaying the image to be displayed according to the compensation gray scale value corresponding to each channel of each of the pixels.

Abstract: Disclosed are a chip verification structure, a chip verification system, and a chip verification method. The chip verification structure includes an analog chip, the analog chip includes at least one analog module. Since the analog chip is homologous with the sample of the chip design, a functional difference between the analog chip and the analog function module of the chip design may be reduced. Since the analog chip is connected to the FPGA chip via the plurality of types of interfaces, a difference between an interface of the analog chip and the FPGA chip and an interface of the analog function module and the digital function module of the chip design may be reduced, so that a verification accuracy of the chip design may be improved and a verification period of the chip design may be reduced.

Abstract: An unlocking device with a pause function comprises a first moving member having a first protruding portion, a second moving member having a second protruding portion, and a third moving member having a third end portion and a fourth end portion. The second moving member is disposed corresponding to the first moving member. The second protruding portion is disposed cooperated with the first protruding portion. The third end portion is connected to the second moving member. When the fourth end portion of the third moving member contacts a carry body, and a first end portion of a releasing member moves along a first direction towards the housing, the releasing member drives the first moving member to move in the first direction, so the second moving member holds the position of the releasing member by the second protruding portion and the first protruding portion.

Abstract: A portable charger includes a housing, a first plug-in assembly, and a charging assembly. The housing comprises an accommodating cavity and an avoidance recess formed in an outer surface. The first plug-in assembly includes a first plug rotatably connected to the housing and a locking element movably connected to the housing. The first plug is rotatable between a plug-in position where the first plug is protruding out of the outer surface of the housing and a storage position where the first plug is accommodated in the avoidance recess. The locking element is movable between a stop position limiting the rotation of the first plug at the storage position and an unlocking position avoiding from the first plug. The charging assembly includes a battery and a control board both arranged in the accommodating cavity. The control board is electrically connected to the first plug and the battery.

Abstract: It is provided a driving system, a driving method, a computer system and a computer readable medium. The driving system includes: an input circuit configured to receive an input on-chip voltage and output the on-chip voltage; an adjusting circuit configured to automatically detect a present amplitude of the on-chip voltage output by the input circuit and to output a bias voltage corresponding to the present amplitude of the on-chip voltage to a gate of the driven thin film transistor, wherein a source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage. The protection of the transistor gate and the adjusting of a receiver threshold voltage for different I/O (input/output) voltages and levels can be completed through automatic detection of the on-chip voltage and automatic adjusting.

Abstract: A monitoring and early warning system based on the Internet of Things for an ancient building includes an information acquisition system, a service platform and a user side. The information acquisition system is configured to acquire state data of the ancient building and upload the state data to the service platform by means of a 4G/5G gateway. The user side is integrated in a visualization device for a user to manage, analyze and interact with the acquired ancient building data, and the user side includes a monitoring module, a pre-alarm module, a management module and an expert module. The service platform is of a duster system integrating a plurality of applications, caches and database servers. The expert module is of a Res-long short-term memory (Res-LSTM) neural network model for evaluating a crack state of the ancient building.

Abstract: A pulse width clock topology structure circuit, comprising a clock pulse width generation module and a clock topology delay module. The clock pulse width generation module connects an input clock and n stages of delay sub-modules in series; an output end of each stage of delay sub-module is connected to an input end of a selector; a certain required delay clock is selected by means of m+1 control signals of the selector, and an “AND” operation is performed on the required delay clock and an original input clock to generate different pulse width clock outputs as inputs of the clock topology delay module; and the clock topology delay module can generate a plurality of different delay clocks for different latches to use.