Patents Assigned to Design & Manufacturing Corporation
  • Patent number: 9307189
    Abstract: A relay apparatus (10) is provided with: an image output unit (11); switches (SWa, SWb); a control unit (16) for controlling switches; and an obtaining unit (16) for obtaining a first CEC address associated with the relay apparatus if the relay apparatus is connected to an output apparatus (30). The control unit controls switches to select a signal channel connecting a first signal transmitting device (14) and a storage apparatus (20) if the first CEC address and a reproduction command are received. After connecting the relay apparatus and a unit (40), the control unit controls switches to select the signal channel connecting the first signal transmitting device and a second signal transmitting device (15) if the unit is in a video output state, and controls switches to select the signal channel connecting the first signal transmitting device and the image output unit if the unit is in a standby state.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: April 5, 2016
    Assignee: PIONEER DIGITAL DESIGN AND MANUFACTURING CORPORATION
    Inventors: Yasuhiro Rin, Takeshi Hashimoto, Yoshiyuki Shimizu, Satoshi Saitoh, Shinichiro Kinoshita, Tomoo Nishigaki
  • Publication number: 20150215575
    Abstract: A relay apparatus (10) is provided with a first signal transmitting device compliant with one second signal transmitting device compliant with another standard, a first obtaining device, a second obtaining device, a generating device and a controlling device. If the relay apparatus is connected to an output apparatus via the first signal transmitting device and is connected to a first unit via the second signal transmitting device, the first obtaining device obtains first information about the first unit; a second obtaining device obtains second information about a second unit connected to the output apparatus; a generating device generates third information that allows selection and operation of each of first and second units, on the basis of first and second information, and transmits the third information to the output apparatus; and a controlling device controls the first unit according to a command signal outputted from the output apparatus.
    Type: Application
    Filed: May 11, 2012
    Publication date: July 30, 2015
    Applicant: Pioneer Digital Design and Manufacturing Corporation
    Inventors: Yasuhiro Rin, Mamoru Oda, Takeshi Hashimoto, Yukitaka Shimizu, Satoshi Saito, Shinichiro Kinoshita, Tomoo Nishigaki, Akio Hosokawa
  • Publication number: 20150089498
    Abstract: A system and method for providing access to a Logical Unit mapped to an iSCSI target are described herein. In accordance with this disclosure, an initiator IQN name may be split into a physical IQN name (PIN) and a virtual IQN name (VIN). The VIN may be assigned to a virtual adapter that is created in a guest partition. The PIN may be assigned to a physical adapter (e.g., an iSCSI initiator in a hypervisor). The physical adapter may log into the iSCSI target on behalf of the virtual adapter using the VIN. The physical adapter may receive a list of available logical units associated with the iSCSI target and map the list of available logical units to the virtual adapter. Thereafter, a quality of service between the virtual adapter and the iSCSI target may be monitored.
    Type: Application
    Filed: November 11, 2013
    Publication date: March 26, 2015
    Applicant: Emulex Design & Manufacturing Corporation
    Inventor: Prabal Krishna
  • Publication number: 20150052280
    Abstract: The current document is directed to offloading communications processing from server computers to hardware controllers, including network interface controllers. In one implementation, the transport channel and zero, one, or more protocol channels immediately overlying the transport channel of a Windows Communication Foundation communications stack are offloaded to a network interface controller. The offloading of communications processing carried out by the methods and systems to which the current document is directed involves minimal supporting development and is configurable, during service-application initialization, by exchange of relatively small amounts of information between an enhanced NIC and the communications stack.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 19, 2015
    Applicant: Emulex Design & Manufacturing Corporation
    Inventor: David Craig Lawson
  • Patent number: 8947989
    Abstract: A wobble determining apparatus is provided with: a calculating device for calculating (i) a first time required until reaching a number of revolutions of a motor which allows a predetermined linear velocity, and (ii) a second time required to move an optical head to a position which allows the predetermined linear velocity, on the basis of the number of revolutions of the motor and the position of the optical head; a judging device for judging whether to keep the optical head in accordance with the calculated first time and the calculated second time; and a controlling device for controlling a moving device not to move the optical head if it is judged to keep the optical head, and for controlling the moving device to move the optical head to the position which allows the predetermined linear velocity if it is judged not to keep the optical head.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: February 3, 2015
    Assignee: Pioneer Digital Design and Manufacturing Corporation
    Inventors: Takashi Tani, Yoshinori Kajiwara, Wataru Terui, Takahiro Otomo
  • Publication number: 20140280716
    Abstract: When interfacing with a host, a networking device can handle a first data like Bulk Data Send. In response to a first doorbell ring, the networking device can read a first queue entry from a send queue in the host. Based on the first queue entry, the networking device can read the first data from a first memory in the host and then output the read first data. The networking device can also handle a second data like Direct Packet Push. The networking device can store a second data received from the host. In response to a second doorbell ring, the networking device can output the second data. The first data and the second data can be associated with first and second queue entries, both on the same send queue in the host. High-throughput and low-latency can be achieved. Small and large data packets can be accommodated.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Emulex Design & Manufacturing Corporation
    Inventors: Sujith ARRAMREDDY, Anthony Hurson, Ashwin Kamath, Jayaram K. Bhat, James D. Butler
  • Publication number: 20140280674
    Abstract: When interfacing with a host, a networking device can handle a first data like Bulk Data Receive. The networking device can receive the first data and read a first queue entry from a receive queue in the host memory. In response to the read first queue entry, the networking device can write the first data to an unpinned memory in the host memory. The networking device can also handle a second data with a Receive Packet in Ring (RPIR) queue. The networking device can receive the second data and write the second data to a pinned memory in the host memory. The RPIR queue can be separate from or overlaid on the receive queue. High throughput and low-latency operation can be achieved. The use of a RPIR queue can facilitate the efficiency of resource utilization in the reception of data messages.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Emulex Design & Manufacturing Corporation
    Inventors: Sujith ARRAMREDDY, Ashwin Kamath, Anthony Hurson, Ravindra S. Shenoy, Chaitanya Tumuluri, Ganesh Boddapati
  • Publication number: 20140282551
    Abstract: Network virtualization can be provided via network I/O interfaces, which may be partially or fully aware of the virtualization. Network virtualization can be reflected in the use of a first header and an additional header(s) for a data frame. A partially-aware transmit example can gather together data frame components, including its additional header(s), via a work queue entry. A fully-aware transmit example can refer to a transmit-side table to gather its additional header(s) and can track the state of its additional header(s) stored in a cache. A partially-aware receive example can handle an additional header(s), e.g., by writing it to host-memory. A fully-aware receive example can determine values from multiple headers (including its additional header(s)) to further determine where to write a data payload to host-memory. The examples can relieve a host's hypervisor from performing all the network virtualization processing. The fully-aware examples can incorporate JOY techniques.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: Emulex Design & Manufacturing Corporation
    Inventors: Sujith ARRAMREDDY, Chaitanya TUMULURI, Jayaram K. BHAT
  • Publication number: 20140281022
    Abstract: A scheduler is disclosed. The scheduler can include a time-wheel structure configured to hold scheduling elements, an enqueuer configured to place a scheduling element on the time-wheel structure, and a delay manager configured to direct the scheduling element through the time-wheel structure and remove the scheduling element from the time-wheel structure. The time-wheel structure can include a plurality of decades that can rotate, and each of the plurality of decades can rotate respectively at one or more different rates of rotation. Multiple scheduling elements can be on the time-wheel structure at least partially during the same time. The scheduling elements can be on different decades or on the same decade. One of the plurality of decades can comprise an entry configured to hold a plurality of scheduling elements.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Emulex Design & Manufacturing Corporation
    Inventors: Sujith ARRAMREDDY, Anthony HURSON, Michael J. ENZ, Daniel B. REENTS, Randall L. FINDLEY, Ashwin KAMATH
  • Patent number: 8792319
    Abstract: A recording medium is provided with: a guide layer on which a guide track or guide tracks are formed; and recording layers, wherein (i) an information mark group and (ii) a distinctive mark group are formed in the guide layer, the information mark group being formed on each of a plurality of guide tracks, the distinctive mark group distinguishing a center track out of the plurality of guide tracks on each of which the information mark group is formed, the distinctive mark group including a pair of distinctive record marks which are shifted toward a right side and a left side, respectively, from a track center of the center track, a width of each distinctive record mark is twice or more a width of the guide track.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: July 29, 2014
    Assignees: Pioneer Corporation, Memory-Tech Holdings Inc., Pioneer Digital Design and Manufacturing Corporation
    Inventors: Takuya Shiroto, Masayoshi Yoshida, Hideki Kobayashi, Masakazu Ogasawara, Takao Tagiri, Makoto Suzuki
  • Publication number: 20140095741
    Abstract: Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.
    Type: Application
    Filed: December 2, 2013
    Publication date: April 3, 2014
    Applicant: Emulex Design & Manufacturing Corporation
    Inventors: Daming Jin, Vuong Cao Nguyen, Sam Shan-Jan Su, John Sui-Kei Tang, Peter Mark Fiacco
  • Publication number: 20140089735
    Abstract: The collection of performance data at multiple servers in a SAN and forwarding that data to a centralized server for analysis is disclosed. Remote agents and a central server application collect specific interesting negative event data to enable a picture of the operational health of the SAN to be determined. The agents are placed in servers having HBAs acting as initiators. The agents interact with the HBAs through a driver stack to collect event data. Because of the initiator function they perform, HBAs have visibility to parts of the network that other entities do not have access to, and thus are ideal locations for gathering event data. A SAN diagnostics manager then pulls the collected data from each agent so that a “picture” of the SAN can be developed. In addition to collecting initiator data, the agents also collect errors and performance data from the OS of the servers.
    Type: Application
    Filed: December 2, 2013
    Publication date: March 27, 2014
    Applicant: Emulex Design & Manufacturing Corporation
    Inventors: David Michael Barrett, Erick Crowell, Bino Joseph Sebastian, John Peter Waszak
  • Publication number: 20140082244
    Abstract: Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.
    Type: Application
    Filed: November 22, 2013
    Publication date: March 20, 2014
    Applicant: Emulex Design & Manufacturing Corporation
    Inventors: Qiang Liu, Allen Russell Andrews, David Bradley Baldwin
  • Patent number: 8675639
    Abstract: A system and method for connecting Ethernet networks is provided. The system includes a port, a port control module, and a connectivity module. The port control module supports a first link speed and can transfer data to ports that support a second or third link speed. The connectivity module can affect the transfer of data between the first port and at least one other port. The connectivity module supports a fixed data transfer rate.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: March 18, 2014
    Assignee: Emulex Design and Manufacturing Corporation
    Inventor: Stuart B. Berman
  • Patent number: 8635387
    Abstract: Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: January 21, 2014
    Assignee: Emulex Design & Manufacturing Corporation
    Inventors: Qiang Liu, Allen Russell Andrews, David Bradley Baldwin
  • Patent number: 8635376
    Abstract: The collection of performance data at multiple servers in a SAN and forwarding that data to a centralized server for analysis is disclosed. Remote agents and a central server application collect specific interesting negative event data to enable a picture of the operational health of the SAN to be determined. The agents are placed in servers having HBAs acting as initiators. The agents interact with the HBAs through a driver stack to collect event data. Because of the initiator function they perform, HBAs have visibility to parts of the network that other entities do not have access to, and thus are ideal locations for gathering event data. A SAN diagnostics manager then pulls the collected data from each agent so that a “picture” of the SAN can be developed. In addition to collecting initiator data, the agents also collect errors and performance data from the OS of the servers.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: January 21, 2014
    Assignee: Emulex Design & Manufacturing Corporation
    Inventors: David Michael Barrett, Erick Crowell, Bino Joseph Sebastian, John Peter Waszak
  • Patent number: 8631169
    Abstract: Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: January 14, 2014
    Assignee: Emulex Design & Manufacturing Corporation
    Inventors: Daming Jin, Vuong Cao Nguyen, Sam Shan-Jan Su, John Sui-Kei Tang, Peter Mark Fiacco
  • Publication number: 20130346799
    Abstract: Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.
    Type: Application
    Filed: August 26, 2013
    Publication date: December 26, 2013
    Applicant: Emulex Design & Manufacturing Corporation
    Inventors: Bruce Gregory WARREN, Carl Joseph MIES, William Eugene MORGAN, William Patrick GOODWIN
  • Publication number: 20130340042
    Abstract: Embodiments of the invention are directed to automatically populating a database of names and secrets in an authentication server by sending one or more lists of one or more names and secrets by a network management software to an authentication server. Furthermore, some embodiments provide that the lists being sent are encrypted and/or embedded in otherwise inconspicuous files.
    Type: Application
    Filed: August 19, 2013
    Publication date: December 19, 2013
    Applicant: Emulex Design & Manufacturing Corporation
    Inventor: Larry Dean HOFER
  • Publication number: 20130322227
    Abstract: A recording medium is provided with: a guide layer on which a guide track or guide tracks are formed; and recording layers, wherein (i) an information mark group and (ii) a distinctive mark group are formed in the guide layer, the information mark group being formed on each of a plurality of guide tracks, the distinctive mark group distinguishing a center track out of the plurality of guide tracks on each of which the information mark group is formed, the distinctive mark group including a pair of distinctive record marks which are shifted toward a right side and a left side, respectively, from a track center of the center track, a width of each distinctive record mark is twice or more a width of the guide track.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 5, 2013
    Applicants: Pioneer Corporation, Pioneer Digital Design and Manufacturing Corporation, Memory-Tech Holding Inc.
    Inventors: Takuya SHIROTO, Masayoshi YOSHIDA, Hideki KOBAYASHI, Masakazu OGASAWARA, Takao TAGIRI, Makoto SUZUKI