Abstract: In a CMOS circuit having at least a first subcircuit coupled between a first point of potential and a first circuit node, and having a second subcircuit coupled between a second circuit node and a second point of potential, said first and second circuit nodes being coupled together, the improvement in combination therewith, comprising: first circuit means coupled to the first point of potential for converting the first potential to a third potential as a function of the magnitude of said first potential, said third potential being of a value inbetween the first and second potentials; a FET having source, drain, gate and well terminals, said source terminal being coupled to said well terminal and to said first circuit node, said third potential being applied to said gate terminal, said drain terminal being coupled to said second circuit node; wherein said FET, in conjunction with said first circuit means, operates to selectively provide a difference in potential between said first and second circuit nodes, the

Abstract: The frequency of a signal is classified in at least two nonoverlapping frequency ranges using the variable frequency of a clock signal as a reference. The clock signal is applied to the count input of a first up counter, and the signal to the reset input of this up counter and to the enable input of a first buffer. The parallel inputs of the first buffer are connected to the count outputs of the up counter, and the parallel outputs of this buffer are coupled to the parallel inputs of a multiple comparator in which each nonoverlapping frequency range is assigned a digital output. Each of these digital outputs is connected to the D input of a D flip-flop, which is clocked by the signal, and to one of the two inputs of an EXOR gate having its other input connected to the Q output of the associated flip-flop.