Patents Assigned to Device Dynamics Lab Co., Ltd.
  • Publication number: 20260247650
    Abstract: A power semiconductor device includes a substrate layer, a semiconductor layer, a barrier layer, a source structure, a drain structure, first and second gate structures, and a field plate that cooperatively form an equivalent circuit including first and second transistors, and a Schottky diode. The barrier layer and the semiconductor layer cooperatively form a 2DEG. The first gate structure controls presence and movement of the 2DEG for controlling a current flow between the source structure and the drain structure. The second gate structure cooperates with the barrier layer to form a diode structure with Schottky diode characteristics. A drain terminal of the first transistor is electrically connected to a source terminal of the second transistor. A gate terminal of the second transistor is electrically connected to a cathode of the Schottky diode. An anode of the Schottky diode is electrically connected to a source terminal of the first transistor.
    Type: Application
    Filed: February 12, 2026
    Publication date: August 20, 2026
    Applicant: Device Dynamics Lab Co., Ltd.
    Inventors: Ming-Cheng LIN, Chao-Ta FAN, Chih-Kai CHANG
  • Publication number: 20260244230
    Abstract: A power circuit includes a reference terminal, a power supply terminal for receiving a power supply voltage, an input terminal for receiving a driving signal, a power semiconductor device electrically connected between the power supply terminal and the reference terminal, an enhancement-mode transistor, and a depletion-mode transistor. The power semiconductor device has a source terminal and a gate terminal. The enhancement-mode transistor has a drain terminal electrically connected to the gate terminal of the power semiconductor device, and a gate terminal and a source terminal that are electrically connected to the input terminal. The depletion-mode transistor has a drain terminal electrically connected to the gate terminal of the power semiconductor device, a gate terminal electrically connected to the source terminal of the power semiconductor device, and a source terminal electrically connected to the input terminal.
    Type: Application
    Filed: February 12, 2026
    Publication date: August 20, 2026
    Applicant: Device Dynamics Lab Co., Ltd.
    Inventors: Ming-Cheng LIN, Chao-Ta FAN, Chih-Kai CHANG
  • Patent number: 11698404
    Abstract: A universal switching platform is configured to test a device under test, and includes a first power source, a first switch, a second switch and a second power source. The first switch, the second switch and the second power source are coupled in series between positive and negative terminals of the first power source. The common node of the first and second switches and the negative terminal of the first power source are configured to be respectively coupled to first and second terminals of the device under test. The universal switching platform provides a voltage and a current to test the device under test when the first and second switches are controlled to transition between conduction and non-conduction.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: July 11, 2023
    Assignee: Device Dynamics Lab Co., Ltd.
    Inventor: Ming-Cheng Lin
  • Patent number: 11528024
    Abstract: A level adjusting circuit includes a parallel resistor-capacitor (RC) sub-circuit, a first diode and an adjustable voltage supply. The RC sub-circuit includes an input capacitor and an input resistor, and includes an input node electrically connected to a driving signal source for receiving a driving signal therefrom, and an output node that outputs an adjusted driving signal. The first diode and the adjustable voltage supply are electrically connected, and are further electrically connected to the output node and a reference voltage node, respectively.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 13, 2022
    Assignee: Device Dynamics Lab Co., Ltd.
    Inventor: Ming-Cheng Lin
  • Patent number: 11522540
    Abstract: A gate-driving circuit includes a unidirectional module and two driving modules, and has a low-potential terminal, an output terminal, and two input terminals via which two driving signals are received. Each of the driving modules includes a capacitor and a resistor that are connected in parallel and between the output terminal and the respective one of input terminals, a power source that is connected between the output terminal and the low-potential terminal, and a diode that is connected between the output terminal and the power source. The unidirectional module is connected between the output terminal and one of the driving modules, and allows an electrical signal to pass only from the one of the driving modules to the output terminal.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 6, 2022
    Assignee: Device Dynamics Lab Co., Ltd.
    Inventor: Ming-Cheng Lin
  • Publication number: 20220221503
    Abstract: A universal switching platform is configured to test a device under test, and includes a first power source, a first switch, a second switch and a second power source. The first switch, the second switch and the second power source are coupled in series between positive and negative terminals of the first power source. The common node of the first and second switches and the negative terminal of the first power source are configured to be respectively coupled to first and second terminals of the device under test. The universal switching platform provides a voltage and a current to test the device under test when the first and second switches are controlled to transition between conduction and non-conduction.
    Type: Application
    Filed: October 8, 2021
    Publication date: July 14, 2022
    Applicant: Device Dynamics Lab Co., Ltd.
    Inventor: Ming-Cheng LIN