Abstract: A drive control system for a microprocessor comprises a switching circuit 5 for varying a drive condition of the microprocessor by varying a processing speed and a power consumption in mutually related manner, an operational state dependent control portion including a status judgment circuit 7, an address monitoring circuit 8, and an address detecting circuit 9, for monitoring the operational state of the microprocessor and controlling the switching circuit 5 for adapting the processing speed to the operational state, and a temperature dependent control portion comprising a temperature sensor 10 and a comparator 11, for lowering the power consumption of the microprocessor when the temperature condition of the microprocessor higher than a predetermined criterion temperature is detected.

Abstract: A power saving control system for a computer system including a CPU, is provided with a mode selecting circuit for selectively operating the CPU in a first mode with relatively high performance and high power consumption and a second mode with relatively low performance and low power consumption, a repeated access detecting circuit for monitoring addresses accessed by the CPU over a given period in order to detect a predetermined operational state of the CPU, in which only specific address group is repeatedly accessed, a control circuit associated with the first means for normally operating the first means in the first mode and responsive to the second means detecting the predetermined operational state, for operating the first means in the second mode as long as the predetermined operational state is maintained, and a state display for generating an indication perceptible by an operator of the computer system indicating current operational mode of the CPU.

Abstract: A power saving control system for a computer system including a CPU, comprises a mode selecting circuit for selectively operating the CPU in a normal mode with relatively high performance and high power consumption and a power saving mode with relatively low performance and low power consumption, a first monitoring circuit for monitoring addresses accessed by the CPU over a first given period in order to detect a predetermined operational state of the CPU, in which only specific address group is repeatedly accessed, a second monitoring circuit for monitoring addresses accessed by the CPU over a second given period in order to detect a predetermined operational state of the CPU, in which only specific address group is repeatedly accessed, the second given period being independent of the first given period and much longer than the first given period, and a controller associated with the mode selecting circuit for normally operating the mode selecting circuit in the normal mode and responsive to one of the first

Abstract: To reduce the total power consumption of a computer system, a supervisory control method is used to detect a substantial rest state of a CPU wherein it is waiting for a substantial task to start while repeatedly executing a small loop program. The method includes a step addresses accessed by the CPU in a predetermined period of time Ta are stored in proper address blocks, the stored addresses being defined as a learned address, and a step wherein a check is made to see if the CPU accesses an address other than the learned address in a predetermined period of time Tb. When no access of the CPU to any address other than the learned address is detected in the checking step, the both steps are repeated until it is detected in the checking step that an address other than the learned address is accessed by the CPU. In this instance, at least the time Ta is reduced for each repetition of the both steps.

Abstract: To reduce the total power consumption of a computer system, a supervisory control method is used to detect a substantial rest state of a CPU wherein it is waiting for a substantial task to start while repeatedly executing a small loop program. The method includes a step addresses accessed by the CPU in a predetermined period of time Ta are stored in proper address blocks, the stored addresses being defined as a learned address, and a step wherein a check is made to see if the CPU accesses an address other than the learned address in a predetermined period of time Tb. When no access of the CPU to any address other than the learned address is detected in the checking step, the both steps are repeated until it is detected in the checking step that an address other than the learned address is accessed by the CPU. In this instance, at least the time Ta is reduced for each repetition of the both steps.

Abstract: The electric power unit of the present invention for a battery-powered electronic appliance comprises a chopper-controlled nonisolated DC-DC converter for converting the output voltage of a battery into required voltage, a bypass switch for bypassing the DC-DC converter, a comparator for comparing the output voltage of the battery with a reference voltage corresponding to the required voltage of the load circuit, and a controller for controlling the bypass switch on the basis of the output signal of the comparator. When the output voltage of the battery is higher than the reference voltage, the battery is connected directly to the load circuit, so that the power of the battery can be supplied to the load circuit without loss due to the operation of the DC-DC converter.