Abstract: A bus system is proposed, which includes M (M is a natural number) master ports, N (N is a natural number) slave ports, a bus, A (A is a natural number) masters, B (B is a natural number) salves, and an internal memory. The bus system includes P (P is a natural number, P?M) master ports, a traffic monitoring unit, Q (Q is a natural number, Q?N) slaves, a port traffic monitoring unit, and a memory clock scaling unit. Accordingly, in a system-on-chip using a low-power processor, a memory clock of an internal memory connected to a plurality of slave ports is scaled so as to distribute bus traffic.