Abstract: A device driver architecture that couples an operating system to a computer interface of a controller device that includes a plurality of functional sub-elements. The device driver includes a plurality of operating system interface objects each presenting an operating system interface (OSI) to the operating system, a plurality of computer interface objects each providing for the generation of programming values to be applied to the computer interface to establish the operating mode of a respective predetermined sub-element of the controller device, and a device driver library of processing routines callable by each of the plurality of operating system interface objects to process data and generate calls to the plurality of computer interface objects in predetermined combinations. The device driver library enables the selection of an execution contexts within which to define the generation and application of the programming values to the computer interface.

Abstract: A device driver architecture that couples an operating system to a computer interface of a controller device that includes a plurality of functional sub-elements. The device driver includes a plurality of operating system interface objects each presenting an operating system interface (OSI) to the operating system, a plurality of computer interface objects each providing for the generation of programming values to be applied to the computer interface to establish the operating mode of a respective predetermined sub-element of the controller device, and a device driver library of processing routines callable by each of the plurality of operating system interface objects to process data and generate calls to the plurality of computer interface objects in predetermined combinations. The device driver library enables the selection of an execution contexts within which to define the generation and application of the programming values to the computer interface.

Abstract: A system is disclosed that includes a plurality of processors, which in some embodiments include DSPs and other microprocessors, and a distributed uniform memory. The distributed uniform memory is subdivided into a plurality of addressable memory spaces each of which are respectively primarily associated with one of the processors in the plurality of processors. At least an addressably contiguous portion of the addressable memory space primarily associated with one processor is mapped into the addressable memory space primarily associated with another processor. Thus, a processor will have access to the addressable memory space primarily associated with another processor, but will have such access independent of the load and timing requirements of the other processors.

Abstract: A system is disclosed that includes a first processor, which in some embodiments includes a DSP, and a first memory pool and a second memory pool. The second memory pool is primarily associated with the DSP and stores code that is available for execution by the DSP. A plurality of code modules are stored in the first memory pool, which in some embodiments is associated with a second processor. The code modules are individually and dynamically swapped into the first memory pool, which in some embodiments is not large enough to simultaneously store all of the code modules. In some instances, the dynamic code module swapping is done at the direction of a second processor, which is aware of the state of the DSP execution. In other instances, the dynamic code module swapping is done at the direction of the DSP. In each instance, dynamic code swapping is performed in a manner that minimizes or eliminates any halts in DSP instruction execution.

Abstract: A portable display tablet is operated in conjunction with a base computer system including a host processor for executing an application program with a predetermined operational function that generates predetermined graphics data and operates in response to predetermined input data. The computer system includes a wireless data transceiver coupled to the processor that is capable of communicating the predetermined graphics and input data between the computer and portable display tablet.

Abstract: The invention is a method and apparatus of a graphic request management system which provides for storing in the header of bitmaps indicative of the last time a bitmap was included in a request as a destination or source bitmap. Where the system determines that a request is to be processed by a graphic coprocessor, the system updates the bitmap headers of the bitmaps included in that request when that request is stored in the queue of the graphic coprocessor. Where the system determines that a request is to be processed by the CPU, the system holds that request until the last operation on any bitmap included in that request, which could effect the results of the request, has been completed by the graphic coprocessor. The request, if only containing source bitmaps, is processed by the CPU immediately after the completion of any writing into all of the source bitmaps due to request stored in the queue.

Abstract: A system in accordance with the invention allows a signal processing system to be configured to perform almost any signal processing function. Such a system includes a redefinable signal processing subsystem and a function-specific module. The system can be defined to perform a particular function by attaching a function-specific module to the redefinable subsystem and downloading function-defining code into the subsystem. The redefinable subsystem includes at least a DSP, a local memory interface, a host interface, and a function module interface. The function-specific module includes at least a subsystem interface, an identifier storage unit, a signal format converter, and a communication adapter. In operation, after a function-specific module is coupled to the subsystem, the subsystem receives a function identifier from the identifier storage unit on the module. The subsystem then requests and receives function-defining code from a host.

Abstract: A system in accordance with the invention allows a signal processing system to be configured to perform almost any signal processing function. Such a system includes a redefinable signal processing subsystem and a function-specific module. The system can be defined to perform a particular function by attaching a function-specific module to the redefinable subsystem and downloading function-defining code into the subsystem. The redefinable subsystem includes at least a DSP, a local memory interface, a host interface, and a function module interface. The function-specific module includes at least a subsystem interface, an identifier storage unit, a signal format converter, and a communication adapter. In operation, after a function-specific module is coupled to the subsystem, the subsystem receives a function identifier from the identifier storage unit on the module. The subsystem then requests and receives function-defining code from a host.

Abstract: A portable display tablet is operated in conjunction with a base computer system including a host processor for executing an application program with an operational function that generates graphics data and operates in response to input data. The computer system includes a wireless data transceiver coupled to the processor that is capable of communicating the graphics and input data between the computer and portable display tablet. The portable display tablet includes a graphics display panel for displaying the graphical data, a low power wireless data transceiver providing short range data communication of the graphics and input data between the base computer system and portable display tablet, and a controller, embedded within the portable display tablet and coupled to the low power wireless data transceiver, that executes a control program to process the graphics data to provide the graphical display data to the graphics display panel.

Abstract: A portable display tablet is operated in conjunction with a base computer system including a host processor for executing an application program with a predetermined operational function that generates predetermined graphics data and operates in response to predetermined input data. The computer system includes a wireless data transceiver coupled to the processor that is capable of communicating the predetermined graphics and input data between the computer and portable display tablet.

Abstract: A data channel controller, coupleable to a base computer system including a base memory, for managing the transport of multiple data streams through a base system interface including a first buffer, a pool memory including a plurality of second buffers, and one or more peripheral devices each having a third buffer. An arbiter system is coupled to said pool memory for selectively enabling the transfer of data with respect to a predetermined first buffer in response to first and second request signals. The peripheral devices operate to transport data through their third buffers with respect to a peripheral interfaces characterized as each having a predetermined data transfer rate. The peripheral devices first request signals to the arbiter system under first predetermined conditions with respect to the presence of data in corresponding third buffers to obtain a transfer of data between corresponding second and third buffers.

Abstract: A kit in accordance with the invention is disclosed that allows for simultaneous connectivity of a variety of SCSI devices to a SCSI card via a SCSI bus. Such SCSI devices include internal narrow, internal wide, external narrow, and external wide devices. A kit in accordance with the invention includes a terminator-adapter. The terminator-adapter includes a first wide connector, a second narrow connector, and a wide bus including an upper and lower bus. The upper bus is coupled to the wide connector and is first and second connector as well as a soft terminator. By enabling the soft terminator, the terminator-adapter behaves as a wide bus terminator. By disabling the soft terminator, the terminator-adapter behaves as a wide-to-narrow adapter. A kit in accordance with the invention may further include a wide cable and a SCSI card. In various embodiments, the SCSI card includes a wide internal connector and a narrow internal connector.

Abstract: A system to control and monitor telephony devices that do not digitally interface with a control device, such as a PC, is disclosed. The control device communicates with the telephony device typically via standard telephone cable using tones to convey status and control information.

Abstract: A device driver architecture that couples an operating system to a computer interface of a controller device that includes a plurality of functional sub-elements. The device driver includes a plurality of operating system interface objects each presenting an operating system interface (OSI) to the operating system, a plurality of computer interface objects each providing for the generation of programming values to be applied to the computer interface to establish the operating mode of a respective predetermined sub-element of the controller device, and a device driver library of processing routines callable by each of the plurality of operating system interface objects to process data and generate calls to the plurality of computer interface objects in predetermined combinations. The device driver library enables the selection of an execution contexts within which to define the generation and application of the programming values to the computer interface.

Abstract: The present invention is directed toward the low latency transport of signals demanding rapid communication. In modems utilizing an error-correcting protocol, messages are generally buffered and sent as a data packet. However, the method in accordance with the invention provides for transport of low latency messages without buffering or formation of a data packet, minimizing signal latency. In addition, modems operating in accordance with the invention maintain compatibility with other modems.

Abstract: A device driver architecture that couples an operating system to a computer interface of a controller device that includes a plurality of functional sub-elements. The device driver includes a plurality of operating system interface objects each presenting an operating system interface (OSI) to the operating system, a plurality of computer interface objects each providing for the generation of programming values to be applied to the computer interface to establish the operating mode of a respective predetermined subelement of the controller device, and a device driver library of processing routines callable by each of the plurality of operating system interface objects to process data and generate calls to the plurality of computer interface objects in predetermined combinations. The device driver library enables the selection of an execution contexts within which to define the generation and application of the programming values to the computer interface.

Abstract: A multiple data stream channel controller providing demand driven transport of multiple data streams concurrently in real time through a peripheral data channel coupled between a general purpose processor system and a special purpose processor system. The controller comprises a first bus master interface coupleable to a general purpose processor system bus, a second bus master interface coupleable to a special purpose processor system bus, a segmentable buffer memory and a controller that directs the transfer of data segments between the first and second bus master interfaces via the segmentable buffer memory. The controller is responsive to a plurality of signals provided by the special purpose processor bus to request transfer of successive data segments from a respective plurality of data streams staged in the segmentable buffer memory.

Abstract: A data transfer control system including a pool memory, a plurality of peripheral devices, and a transfer controller. The pool memory provides for the storage of data in a plurality of FIFOs formed within the pool memory. The plurality of peripheral devices are coupleable to the pool memory to provide for the transfer of data between programmatically associated FIFOs and peripheral devices. The transfer controller is coupled to the pool memory and to the peripheral devices for selectively managing the transfer of data between the FIFOs and the peripheral devices. The transfer controller includes a distributed signaling system coupled to the peripheral devices to permit the broadcast of status information reflective of a transfer of data relative to a predetermined FIFO to the peripheral devices.

Abstract: A bus transfer control system manages the transfer of multiple asynchronous data streams through a buffer pool. The bus transfer control system includes a buffer pool having a plurality of memory blocks, wherein each memory block provides for the storage of a plurality of data bytes and a plurality of data transfer devices coupled to the buffer pool to allow the transfer of segments of one or more data streams to be transferred between the plurality of data tranfer devices through the buffer pool. A transfer controller maintains status information relating to the status of data in the memory blocks and includes control logic for repeatedly evaluating the status information and providing for the prioritied selection of a first data transfer device and a predetermined one of the memory blocks.

Abstract: A device driver architecture that couples an operating system to a computer interface of a controller device that includes a plurality of functional sub-elements. The device driver includes a plurality of operating system interface objects each presenting an operating system interface (OSI) to the operating system, a plurality of computer interface objects each providing for the generation of programming values to be applied to the computer interface to establish the operating mode of a respective predetermined sub-element of the controller device, and a device driver library of processing routines callable by each of the plurality of operating system interface objects to process data and generate calls to the plurality of computer interface objects in predetermined combinations. The device driver library enables the selection of an execution contexts within which to define the generation and application of the programming values to the computer interface.