Abstract: The disclosure describes integrated circuits and training apparatuses for efficiently training learnable logic networks. One or more hardware-implemented learnable logic engines execute forward and backward propagation through differentiable relaxations of Boolean logic gates arranged in configurable clusters. Each engine processes multiple inputs and outputs with shared parameter sets, supports variable numbers of gate inputs, and may reuse locally stored parameters across batched samples to reduce memory bandwidth. Engines and associated cores employ mixed-precision arithmetic, including low-precision activations and higher-precision gradients with on-chip gradient accumulation. Configurable interconnects route activations between engines, and topology bits select among logic operations and wiring options. Systems including a host processor orchestrate the use of the learnable logic engines to design fixed logic gate networks for efficient inference.