Abstract: Data compression, for either a storage or transmission, of facsimile information is effected employing a two dimensional, non-contiguous prediction matrix. A data stream representing the data to be compressed is input to a buffer which is of a size to store sufficient information for prediction purposes. A predictor is responsive to the buffer for producing a predicted data representation from a plurality of data units comprising a two dimensional matrix. A selector is responsive to the data unit employed in the prediction process for making a select/non-select determination. For those data units which are selected, a comparator compares the predicted status of the data unit with the actual status of the data unit. At least one run length encoder is responsive to the comparator for run length encoding successive correct predictions and a following incorrect prediction.

Abstract: An on-line channel monitor, for measuring E.sub.b /N.sub.O, measures the quality of a communication channel while the channel is in use. The channel monitor employs a soft-decision demodulator so as to compare analog signal levels of an AGC compensated signal in a demodulator with the desired signal level. Deviations, termed pseudo-errors, are counted and the number of counts integrated. The result is employed to drive a meter calibrated in terms of E.sub.b /N.sub.O.

Abstract: The digital demodulator produces an information bearing analog signal which is controlled in peak-to-peak amplitude. The signal is coupled to a soft-decision demodulator which provides a multi-bit output representative of magnitude (polarity and amplitude) of the analog signal at a rate determined by the symbol clock derived from the digital demodulator. Logic means produces a logic signal of a first or second type in response to selected multi-bit outputs of the soft-decision demodulator. A logic output of the first type is produced if either the multi-bit output represents an analog signal of one polarity and amplitude greater than a predetermined amplitude, or if the multi-bit output represents an analog signal of the other polarity and amplitude less than an equal predetermined amplitude of the other polarity. The logic output is coupled to an integrating means which produces a control signal representative of deviations of the logic signal of the first type from 50% duty cycle.

Abstract: A TDMA multiplexer-demultiplexer includes a plurality of input/output ports and common control equipment. Each input port is capable of accepting information asynchronous to the TDMA clock and at typical terrestrial clock rates. The input/output ports perform all the necessary signal processing for a TDMA terminal including pulse stuffing, changing continuous asynchronous low rate information to high bit rate burst form as well as forward acting error correcting encoding, if desirable. By incorporating all the signal processing in the multiplexer-demultiplexer, much equipment duplication is eliminated along with eliminating a requirement for multiple high frequency control and timing signal line drivers and buffers. More particularly, the transmit side of each port includes a separate elastic buffer to raise the input rate to a synchronous common higher rate. In addition, on the receive side, clocking on the low speed side of the expansion buffer is derived from the station's transmit clock.

Abstract: An improved phase-locked loop includes a phase detector, active loop filter and a VCO, in conventional phase-locked loop relationship. In addition, a positive feedback path couples active loop filter output to active loop filter input. In the absence of loop lock, the positive feedback provided by the positive feedback path satisfies the conditions necessary for the production of an oscillating output from the active loop filter circuit. The oscillating output generated by this "oscillator" drives the VCO in a sweeping action allowing the loop to acquire signals outside of its normal capture range. On capture, phase detector output provides an additional negative feedback path which overrides the effect of the positive feedback path and therefore, oscillations cease and the loop locks. The positive feedback path can comprise a relatively simple passive frequency selective circuit.

Abstract: A direction phase shift keyed communication system provides the capacity to transmit any one of two symbols for each modulation level. The modulator produces a substantially constant frequency signal which includes a phase transistion in respect of each information bit. In a system with a single modulation level, corresponding to a phase transistion .phi., one of the two symbols is represented by a phase transition +.phi., i.e., an advancing phase transition. The other symbol is represented by a phase transition -.phi., i.e., a retarding phase transition. A demodulator responds to a substantially constant frequency signal with a phase transition included, and produces an output signal of a first kind in response to an advancing phase transition +.phi. and an output signal of a second kind in response to a retarding phase transistion -.phi.. The system is capable of operating with multiple modulation levels, each of which can represent any one of two symbols, depending on the sense, i.e.

Abstract: An in band single channel per carrier supervisory and signalling apparatus and method is disclosed for satellite communications. The apparatus includes a near supervisory interface located at a transmitting terminal, and a far supervisory interface located at a receiving terminal. The near supervisory interface responds to either dc or single tone conventional signalling on a sending telephone line and formats hook status and dial pulse transitions for in band transmission. The far supervisory interface responds to the messages, as formatted by the near supervisory interface and, re-formats the information thus communicated for the receiving telephone system.

Abstract: A communication terminal interface accepts, on different channels, information in a plurality of formats for communication purposes over a communication link which may be a TDMA satellite link. Each channel is accepted by a different interface unit which serves to format the information for communication over the system. This unit includes a compression-expansion buffer memory for allowing information received at a receive rate R.sub.s to be multiplexed and transmitted at a transmission rate T.sub.s which may be many times higher than the receive rate. In addition some units may include forward acting error correcting coding selected to provide the necessary corrected bit error rate for the type of information accepted by the unit and the capacity of the communication link over which the information is to be transmitted. The transmitter may employ differential encoding.

Abstract: A phase locked loop with pre-set and squelch capability particularly adapted for burst type signals. In addition to the conventional phase detector, loop filter (LF) and voltage controlled oscillator (VCO) the loop includes a squelch switch connected between the phase detector and LF. A track and hold circuit is connected in series with another switch between output and input of the LF. Both switches and the track and hold circuit itself are controlled by the output of a level detector which indicates presence of an intermittent (i.e., bursty) carrier. The squelch switch is closed, connecting the phase detector to the LF, when the output of the level detector indicates the presence of a carrier burst. At the same time, the second switch is opened so that the LF is not affected by the output of the track and hold circuit. In addition, the track and hold circuit is enabled to track the error voltage output of the LF.

Abstract: A TDMA system in which each station times its respective data burst from a reference sync burst transmitted by a designated primary reference station over the satellite link. Another station transmits a secondary sync burst timed from the primary stations sync burst. To maintain synchronism at the satellite each station has a burst synchronizer operated by receipt of the primary reference sync burst. The secondary sync burst is also received by each of the stations and is capable of ensuring synchronization in case of failure of the primary stations's sync burst.

Abstract: A frame synchronizer is disclosed for searching for the framing bits of an N bit frame in a stream of binary signals. Means are provided to compare, bit by bit, the signals in different bit positions of two adjacent frames. When only a single bit position indicates an alternating pattern of binary signals, it is considered the framing bit and a framing pulse is provided in that bit position. Apparatus is also provided to detect loss of synchronization including a pair of counters, one counting framing pulses and the other counting alternating signals in that bit position. To reduce the likelihood of false out-of-synchronization signals, the second of these counters can be pre-set. Only when the count of the first counter exceeds the number of signals counted by the second counter by this pre-set quantity will out-of-synchronization be declared.

Abstract: A side lock detector to prevent side lock in coherent PSK demodulation. For demodulation purposes it is necessary to recreate the carrier at the receiver. This may be accomplished with a phase-locked loop. However, with plural phase PSK modulation the input signal to the phase-locked loop has energy at side bands spaced at modulation rate intervals from the desired lock frequency as well as at the desired lock frequency. To detect side band lock, a band pass filter monitors the phase detector output of the phase-locked loop. The center frequency of the filter is equal to the modulation rate and the filter band width is very narrow. Only during side lock will significant amounts of energy pass the filter. This energy may be detected by a simple diode detector or the like. A lock inhibit means is provided, responsive to the output of the detector, to drive the voltage controlled oscillator out of a side lock condition.

Abstract: A clock for locally distributing a synchronized signal derived from a remotely transmitted signal. The clock normally operates in the slave mode, phase locked to the remotely transmitted signal, when that signal is deemed available. If it is not available the clock switches to a master mode in which it independently generates the necessary signal.