Abstract: An arrangement for a multiprocessor RISC system enables each CPU of the system to test the control logic of its cache by indirectly examining states of the caches and comparing those states to predetermined valid cache states of the system. The arrangement includes a plurality of processes configured to acquire information from selected block entries of the caches. The information is then compared with an array of predetermined valid cache states contained in a state table to detect invalid cache states. A cache examining protocol defines the operational procedures followed by the processes when acquiring and examining the information.

Abstract: The set-prediction cache memory system comprises an extension of a set-associative cache memory system which operates in parallel to the set-associative structure to increase the overall speed of the cache memory while maintaining its performance. The set prediction cache memory system includes a plurality of data RAMs and a plurality of tag RAMs to store data and data tags, respectively. Also included in the system are tag store comparators to compare the tag data contained in a specific tag RAM location with a second index comprising a predetermined second portion of a main memory address.

Abstract: A system and method for adaptively managing the behavior of, for example, a digital data processing system, using inductive learning techniques. The new system includes a data acquistion portion that acquires event data in response to selected events. An inductive engine generates profile knowledge in response to acquired event data during a learning phase, for storage in a profile knowledge store. A profile comparator, during an operational phase, subsequent to the learning phase, performs a verification operation in connection with comparing event data to said profile knowledge stored in said profile knowledge store. A control portion enables event data acquired by said data acquisition portion to be directed to the inductive engine during a learning phase and to the profile comparator during an operational phase to thereby permit the comparator to perform a verification operation in connection with said event data acquired during the operational phase.

Abstract: A vector register provides the capability for simultaneously writing through at least two write ports and simultaneously reading from at least two read ports. In addition, a barber pole technique for storing words from logical vector registers into banks is provided to minimize conflicts.