Abstract: A knowledge processing system and a method for operating same for interacting with a user of the system. The system includes a user interface for prompting the user to enter information and for receiving entered information from the user. The user interface is coupled during use to a knowledge model processor (10) that includes a Dialogue Control Interpreter (16) that provides structured messages to a user so as to elicit responses from the user concerning Imperatives of the user, Situations of the user, Knowledge known to the user, and Executive Agents known to the user. This information is stored in a User Awarenesses database (18). The Dialogue Control Interpreter operates in accordance with predetermined dialoguing Imperatives (20) to elicit, record, and access user responses in sequences that guide and motivate the user to follow predetermined sequences of thought, based on the recorded User Awarenesses database of Imperatives, Situations, Knowledge, and Executive Agents.

Abstract: Disclosed is a method for operating a cache memory. In response to a write transaction, data is written to a location in a foreground memory that is part of the cache. A modified bit is set in the foreground memory indicating that the data must be written back to main memory. A registration bit is checked in the foreground memory location to determine whether the address is registered. The location of the foreground memory is written to a registration memory in the cache if the registration bit is not set. The registration bit is set in the foreground memory, in conjunction with writing the address of the memory location to the registration memory, to indicate that the address has been registered. In response to a subsequent transaction, the foreground memory location can be selected to store new required data. The modified bit is checked to determine whether the data stored in the foreground memory location must be written back to main memory before the location can be used to store the new data.

Abstract: The present invention is directed to a programmable logic circuit used as an arbiter to control access to a shared resource, e.g. a system bus, by N devices in a computer system. The programmable arbiter according to the present invention, implements a logic design with sufficient flexibility to accommodate and selectively incorporate features of several different arbitration schemes including a straight priority scheme, a programmable arbitration, and a rotating priority arbitration scheme. In addition to these arbitration schemes, the arbiter of the present invention supports an extended programmable arbitration scheme whereby a device which is requesting access to the shared resource may be granted access to the resource even if it has used up its allocated share of bandwidth if there are no other devices requesting access to the shared resource. Furthermore, bus bandwidth may be allocated to particular device or to a group of devices at a particular priority level.

Abstract: A rule-partitioning system for converting at least a portion of a target expert system program to a rule partitioned RETE network for execution on multiple processors, including a rule partitioning portion for assigning different rules of the target expert system program to different partitions on the basis of previously collected processing statistics and on the use of node sharing; and a compiler for converting the target expert system program to the RETE network, wherein the rules of the RETE network are assigned to the multiple processors in accordance with the partition assignments.

Abstract: A method for translating a virtual address into a physical address, in which page tables used in the translation process are referenced by virtual addresses. Typically, a translation mechanism includes a translation buffer that, given a virtual address, can sometimes provide the corresponding physical address. A translation-buffer miss is said to occur when the translation buffer is presented with an address for which it can not provide the translation. When such a miss occurs, the translation mechanism obtains the translation by reading the page tables. When the translation mechanism attempts to read the page tables from virtual memory, a second-order miss can occur. The difficulty of infinite recursion of misses is avoided by handling second-order misses differently from first-order misses. When a second-order miss occurs, the translation mechanism uses a prototype page table entry and the virtual address of the page table entry to produce a physical address without using the page tables.

Abstract: In a method and a circuit arrangement for recovering a digital signal having digital pulses from a recorded signal which is read by a read head of a storage device, the shape of the recorded signal, being a reproduction of the digital signal, is compared with the shape of a normal read signal previously stored as a comparison pattern of voltage values. In the case of agreement, which is given on the presence of a certain correlation, the recorded signal is evaluated as a digital pulse and otherwise on non-agreement as a digital non-pulse.

Abstract: Differential buffers are used in a voltage-controlled oscillator to provide pairs of complementary phase signals. The preferred arrangement includes a ring of the differential buffers. Each differential buffer has a current control input, and the current control inputs of the buffers are all connected to a control voltage input to simultaneously adjust the propagation delay of each of the buffers. In contrast to a conventional ring oscillator, which has an odd number of stages, a ring oscillator made of differential buffers can have an even number of buffers to provide a number of phases that is a multiple of four. The differential buffer preferably includes a pair of CMOS inverters sharing a common PMOS current sourcing transistor and a common NMOS current sinking transistor.

Abstract: A semiconductor probe and alignment system are disclosed. The semiconductor probe includes a silicon-based substrate and membrane on which a plurality of pyramid shaped contactors are formed. Each of the contactors includes a metalized tip for contacting bonding pads on a semiconductor die. The area of the probe surrounding each contactor is thinned to form a membrane to provide flexibility and thus compliance to assure contact between each contactor and its respective bonding pad. In the alignment system, a guide wall formed from a photo-imageable material is created around at least a portion of each bonding pad to provide alignment for guiding the contactors on the probe onto the bonding pads.

Abstract: An improved arbitration technique for a computer network system in which multiple nodes communicate using a shared bus, and at least one node has no knowledge of the current status of the arbitration taking place between all nodes in the system. Such a node is called a "deaf node". Each node in the system is assigned an initial arbitration count number, for example, N+1, where N is the node number assigned to the node. The arbitration count number is the number of quiet slots a node must count before trying to transmit on the system bus. The length of a quiet slot is determined by a particular system's electrical characteristics. One quiet slot is reserved as the "deaf node quiet slot", during which a deaf node may transmit. In response to a transmission occurring in the deaf node quiet slot, each node in the system reinitializes its arbitration count number to its initial arbitration count number.

Abstract: A digital data management system for managing a shadow set of storage media includes a plurality of storage media each accessible by at least one data processing device for I/O operations. Successive comparisons are carried out between data stored in corresponding locations in the storage media while maintaining access to the storage media for I/O operations. When inconsistency between data in corresponding locations is detected, a management operation is performed on at least one of the shadow set storage media. The management operation includes interrupting I/O operations to at least the storage medium on which the operation is performed, modifying data on one of the shadow set storage media to correct the inconsistency, and resuming availability of the storage media for I/O operations.

Abstract: A memory controller manipulated enqueuing and dequeuing process for singly linked queues in a memory system in response to single exclusive-access write and read commands from any CPU in the associated data processing system.

Abstract: A method and apparatus for converting unstructured descriptions of signal timing constraints, which can be entered by a user in a natural-language format, into unambiguous symbolic specification descriptions. The invention also generates file structures containing both the signal characteristics entered by the user and timing-constraint information that may be derived therefrom.

Abstract: A method of managing the memory of a CM multiprocessor computer system is disclosed. A CM multiprocessor computer system includes: a plurality of CPU modules 11a . . . 11n to which processes are assigned; one or more optional global memories 13a . . . 13n; a storage medium 15a, 15b . . . 15n; and a global interconnect 12. Each of the CPU modules 11a . . . 11n includes a processor 21 and a coupled memory 23 accessible by the local processor without using the global interconnect 12. Processors have access to remote coupled memory regions via the global interconnect 12. Memory is managed by transferring, from said storage medium, the data and stack pages of a process to be run to the coupled memory region of the CPU module to which the process is assigned, when the pages are called for by the process. Other pages are transferred to global memory, if available. At prescribed intervals, the free memory of each coupled memory region and global memory is evaluated to determine if it is below a threshold.

Abstract: In a data processing system a structure (50) called an I/O association is constructed. An I/O association (50) is a symmetric structure which allows not only consumer (52) of a service to locate the provider (54) of the service, but it also permits the converse. In some respects, an I/O channel (32) is only half of an association (50). The association (50) describes a targeted object (56) and provides the means (57) of locating the necessary procedures to operate on the target (56). The association (50) also describes a source object (58) that is held responsible for the requested operation, as well as the means (60) of locating and invoking procedures to report results to the source object (58).

Abstract: A method for determining whether particular information was used in encoding a codeword; the codeword is formed by encoding information as a first preliminary code sequence using a first code and then combining the first preliminary code sequence with a second preliminary code sequence generated using a second code; the particular information is encoded as a desired first preliminary code sequence in accordance with said first code; the desired first preliminary code sequence is then stripped from the codeword to derive a test sequence; the test sequence is decoded in accordance with the second code, and a determination is made, based on the decoding, whether the particular information was used in encoding the codeword.

Abstract: A method and apparatus for a read-modify-write operation in a digital computer memory system that reduces memory data path buffer storage requirements. The method latches new write data and associated mask fields into a data output buffer and then uses the latched mask fields to merge read data with the new data in the output buffer. The mask fields determine which portion of the read data is to be replaced with new data. Appropriate check bits for an error correction code (ECC) are generated and added to the modified data in the output buffer to produce a new data output which is released from the output buffer into the memory at the selected address.

Abstract: A distributed computer system has a number of computers coupled thereto at distinct nodes. The computer at each node of the distributed system has a trusted computing base that includes an authentication agent for authenticating requests received from principals at other nodes in the system. Requests are transmitted to servers as messages that include a first identifier provided by the requester and a second identifier provided by the authentication agent of the requester node. Each server process is provided with a local cache of authentication data that identifies requesters whose previous request messages have been authenticated. When a request is received, the server checks the request's first and second identifiers against the entries in its local cache. If there is a match, then the request is known to be authentic. Otherwise, the server node's authentication agent is called to obtain authentication credentials from the requester's node to authenticate the request message.

Abstract: Semiconductor package and method in which a cavity is provided for a chip or die, a bonding shelf extends peripherally of the cavity, and a layer of metallization extends along the under side of the shelf, wraps around the inner peripheral edge of the shelf and extends along the inner margin of the upper surface of the shelf to form a conductive ring to which a lead from the chip is bonded. Additional bonding pads are formed on the upper surface of the shelf, and additional leads from the chip are attached to these pads. In one embodiment, locating fingers align the chip precisely within the cavity.

Abstract: A decryption method, and associated cryptographic processor, for performing in-line decryption of information frames received from a communication network through a first in-line processing stage. As an information packet is streamed into the cryptographic processor, a determination is made to an acceptable level of probability whether the packet contains data that should be decrypted. The decision whether or not decrypt is made by analyzing the incoming packet header, recognizing a limited number of packet formats, and further parsing the packet to locate any encrypted data and to make sure that the packet is not a segment of a larger message. Falsely decrypted packets are looped back through the cryptographic processor, to regenerate the data that was falsely decrypted. Decryption and encryption are performed in such a manner that a false decryption is completely reversible without loss of data.