Abstract: A digital system has a main memory 10 with a main memory access (DMA) unit 11 through which data channels 12, 13 are coupled to the memory. A processor system (processor 14, RAM data memory 15, instruction memory 16) is also coupled to the memory through a read/write buffer 20, each read stalling the processor for typically 5 cycles. For block reads, a block memory read unit 25 is connected in parallel with the path between the read/write buffer 20 and the DMA unit 11. This block read unit can be set from the processor 14 with a block start address and a block length passed as writes through the read/write buffer 20. The block is read (first phase) word by word from the main memory via the DMA unit into a memory 28 in the block read unit.

Abstract: A method and apparatus for automatically generating validation tests for implementations of a program specification for an operating system, software application or a machine, where the program specification is expressed at least in part in terms of data structures and relationships. The method is carried out by a computer. The program specification is expressed in an interface specification language which is automatically parsed, and is then transformed into an extended finite state machine (EFSM) or multiple-EFSM architecture internally represented in the computer, the EFSM including objects representing states and transitions between those states representing executable functions, annotated to the states. The annotations may represent predicates, test data, value assignments, branch conditions, etc. The EFSM or architecture is traversed by a path traversal procedure, either exhaustively or in part, thereby producing path files, one for each path taken.