Abstract: A direct memory access (DMA) first-in-first-out (FIFO) buffer includes two FIFO devices connected in parallel. An output multiplexer is controlled by a controller to pass to its output data provided by a selected one of the FIFO devices. Data is clocked into one FIFO device until it is full, after which data may be written from it. When data is written from a FIFO device, the FIFO device is emptied before data is again read into it. Using this arrangement, data can be read into one FIFO device whilst data is written from the other FIFO device.

Abstract: A library virtualisation module (LVM) 13 is disclosed, the LVM being configured to connect first and second hosts 11, 12 to a library 14. The LVM comprises least two host input/outputs, each for connection to a respective host; and a library input/output, for connection to the library 14. The LVM 13 is arranged to modify requests received at its host input/outputs and to provide modified requests to the library input/output in such a way as to divide resources of the library 14 between the hosts 11, 12 without requiring unmodified requests to take into account the division of resources.

Abstract: A connection device comprises a first physical device, a first device driver layer, a first interface abstraction layer, in which is embedded a first software support layer, a data core, a second interface abstraction layer, in which is embedded a second software support layer, a second device driver layer and a second physical device. A command and control module is connected to each of the physical devices and to the data core. Data and commands passing from the first device driver layer to the data core are removed of protocol-dependent information.