Abstract: The present disclosure relates to systems and methods of implementing a service manager. In particular, the present disclosure relates to methods of monitoring a plurality of services, wherein each service is uniquely identifiable in a process table based on a fingerprint; receiving a request to add a new service to the plurality of services; determining whether service dependencies in a configuration of the plurality of services and the new service are compatible; and responsive to determining that the service dependencies in the configuration of the plurality of services and the new service are compatible, starting the new service. The method may further include receiving a request to call a user-defined function and determining whether the new service is functional based on executing the user-defined function.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to receive a plurality of non-sequential memory access commands directed to the set of non-volatile memory cells, predict a predicted memory access command based on the plurality of non-sequential memory access commands, and access the set of non-volatile memory cells according to the predicted memory access command.

Abstract: Memory systems that can predict a physical address associated with a logical address, and methods for use therewith, are described herein. In one aspect, the memory system predicts a physical address for a logical address that follows a sequence of random logical addresses. The predicted physical address could be a physical location where the data for the logical address is predicted to be stored. In some cases, the host data can be returned without accessing a management table. The predicted physical address is not required to be the location of the data to be returned to the host for the logical address. In one aspect, the memory system predicts a physical address at which information is stored that may be used to ultimately provide the data for the logical address, such as a location in the management table.

Abstract: The present disclosure generally relates to data storage devices, and more specifically, to a magnetic media drive employing a magnetic recording head. The head includes a trailing shield, a main pole, a MAMR stack disposed between the trailing shield and the main pole, side shields surrounding at least a portion of the main pole, and a structure disposed between the side shields and the main pole at a media facing surface (WS). The structure is fabricated from a material that is thermally conductive and electrically insulating/dissipative. The material has a thermal conductivity of at least 50 W/(m*K) and an electrical resistivity of at least 105 ?*m. The structure helps dissipate joule heating generated from either the main pole or the MAMR stack into surrounding area without electrical shunting, leading to reduced heating or break-down induced failures.

Abstract: Systems and methods for efficiently implementing data protection techniques that protect data stored in volatile and non-volatile memory devices from soft errors are described. The error correction overprovisioning for a plurality of memory banks may be reduced by implementing localized single-bit error parity to detect single-bit errors within each memory bank of the plurality of memory banks and then sharing a single-error correcting parity or a single-error correcting and double-error detecting parity (SECDEC) over multiple memory banks or over all of the plurality of memory banks. The single-error correcting code (e.g., a Hamming code) may be generated and shared over the plurality of memory banks such that the single-error correcting code may correct single-bit errors across multiple sets of data stored within the plurality of memory banks that correspond with a particular line or row across all of the plurality of memory banks.

Abstract: An example of a system includes a host interface, a set of non-volatile memory cells assigned a first logical address range, and one or more control circuits coupled to the host interface and coupled to the set of non-volatile memory cells. The one or more control circuits are configured to generate debug data and send the debug data through the host interface in response to a command received through the host interface. The command is directed to a second logical address range, the second logical address range assigned exclusively for debug data.

Abstract: The subject technology provides for scanning blocks of a flash memory device for erased pages. A first codeword read from a page of a block in a flash memory device is received and provided to a first decoder for decoding. In response to receiving a first success indicator from the first decoder indicating that the first codeword was successfully decoded, first decoded data is provided from the first decoder to a second decoder for verification of the first decoded data. In response to receiving a first failure indicator from the second decoder indicating that the first decoded data was not verified, the page of the block is identified as being in an erased state based on the first success indicator received from the first decoder and the first failure indicator received from the second decoder.

Abstract: Disclosed herein are apparatuses and methods for writing to a magnetic medium, and data storage devices comprising such apparatuses and methods. An apparatus comprises a main pole, a trailing shield, a write-field-enhancing structure, a write coil, a write current control circuit configured to supply a write current to the write coil to record a bit to a magnetic medium, and a driving current control circuit configured to supply a driving current to the write-field-enhancing structure, wherein the driving current comprises a driving pulse. A method of writing to a magnetic medium comprises supplying a write current to a write coil of a magnetic write head, and supplying a driving current to a free layer disposed in a write gap between a main pole and a trailing shield of the magnetic write head, wherein the driving current comprises an AC component.

Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.

Abstract: Systems and methods for processing and arbitrating submission and completion queues are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device processes the commands through various phases including fetching, processing, posting a completion message, and sending an interrupt to the host. The memory device may process the commands based on the determined priority of the command. For example, the memory device may determine a priority for performing the phases after fetching the command. As another example, the memory device may perform the internal command selection based on a priority associated with the command. In this way, commands may be executed based on the priority needs of the memory device or of the host device.

Abstract: A decoder is configured to perform, for a unit of data received by the decoder, a plurality of decoding iterations in which a plurality of messages are passed between a plurality of check nodes and a plurality of variable nodes, each message indicating a degree of reliability in an observed outcome of data. The decoder determines, for each of the plurality of decoding iterations, whether a trigger condition is satisfied based on an internal state of the decoder and, when a trigger condition is determined to be satisfied during a respective decoding iteration, scales one or more respective messages of the plurality of messages during a subsequent decoding iteration. The unit of data is decoded based on the plurality of decoding iterations and at least one scaled message resulting from the trigger condition being satisfied during the respective decoding iteration.

Abstract: The present disclosure describes technologies and techniques for use by a data storage controller (such as a non-volatile memory (NVM) controller) to adaptively throttle the issuance of commands by a host to the controller. In illustrative examples, an NVM controller throttles the insertion of commands by the host into its submission queues to prevent timeouts that might otherwise occur if the NVM controller has slowed its operations (due, for example, to excessive temperatures within the NVM controller) and is thus unable to complete all issued commands within a host timeout interval. In some examples, throttling is achieved by providing the host with an adjusted head pointer set to a value to reduce the depth of the submission queue as observed by the host. Fewer commands are then sent by the host to the NVM controller via the submission queues, reducing the risk of a host timeout. NVMe examples are provided.

Abstract: A sound-attenuation part, such as for use in a rack-mount server, is configured for insertion into an orifice of a backplane to which at least one data storage device is coupled. The sound-attenuation part may include one or more pipes extending from a mounting portion. The sound-attenuation part helps to attenuate acoustic noise, such as from a cooling fan, which might otherwise reach the data storage device, such as through airflow orifices constituent to a backplane that is positioned between the fan and the storage device, while maintaining enough airflow through the backplane for system cooling purposes. Thus, degradation of the head positioning accuracy within the storage device, caused by the forces associated with this acoustic noise, may be reduced.

Abstract: A single-geo system includes a network configuration generator and a first computing system rack, or a multi-geo system includes a network configuration generator, a first computing system rack, and a second computing system rack are described. The system receives network information for a first plurality of nodes and a second plurality of nodes, and generates a system-wide network configuration file including network configuration information for the first plurality of nodes and the second plurality of nodes. Each plurality of nodes includes a controller node to receive the system-wide network configuration file, identify network configuration information for this plurality of nodes in the system-wide network configuration file as being part of the computing system rack, and update network configuration for this plurality of nodes based on the identified network configuration information for the computing system rack.

Abstract: In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.

Abstract: A system on a chip or storage device has a dynamic process for handling system events that are transmitted at varying transmission rates. This dynamic process is a hybrid mode of operation that tailors the use of time stamp information according to the dynamic flow of events that are submitted in the system. Relative time stamps can be used along with explicit time stamps. Periodic wrap around events which use relative time stamps based on the periodic wrap events may be suppressed when there were no events between consecutive wrap around events. When an asynchronous event occurs during the suppression, the event is identified with a high precision time stamp (HPTS) rather than a relative time stamp. The periodic wrap around events can be re-initiated after the HPTS event is stamped.

Abstract: A computer-implemented method for detecting real flash failures in a runtime environment and determining the cause of the failure may include identifying a software parameter and a hardware parameter associated with a flash memory device at runtime; storing the software parameter and the hardware parameter in a failure detector module coupled to the flash memory device; detecting a flash translation layer failure associated with the flash memory device; performing analysis of the software parameter and the hardware parameter stored in the failure detector module by comparing them to predefined thresholds; and determining a cause of the flash translation layer failure based on the performed analysis.

Abstract: Technology is described herein for operating non-volatile storage. In one aspect, a memory controller replaces an original data buffer pointer(s) to a host memory data buffer(s) with a replacement data buffer pointer(s) to a different data buffer(s) in the host memory. The original data buffer pointer(s) may be associated with a specific read command. For example, the original data buffer pointer(s) may point to data buffer(s) to which data for some range of logical addresses (which may be read from the non-volatile storage) is to be transferred by a memory controller of the non-volatile storage. The replacement data buffer pointer(s) could be associated with a different read command. However, it is not required for the replacement data buffer pointer(s) to be associated with a read command. The replacement data buffer pointer(s) may point to a region of memory that is allocated for exclusive use of the memory controller.

Abstract: Technology disclosed herein efficiently uses memory available in non-volatile storage devices in a non-volatile memory system. In one aspect, a manager collects enough data to fill an entire chunk of a redundancy coding stripe, and requests that the entire chunk be written together in a selected non-volatile storage device. The selected non-volatile storage device may return an internal address at which the entire chunk was written. The manager may store a stripe map that identifies the internal addresses at which each chunk was stored.

Abstract: Techniques for distributing data in a distributed data storage system using a hierarchy rule that is generated based on a spreading policy and a set of tolerable failures specified by a user in absence of system deployment information are disclosed. The system includes a controller node which receives a request including a spreading policy and a protection level for spreading a first data object. The controller node determines a hierarchy rule corresponding to the spreading policy based on the protection level. The controller node distributes the first data object in the system using the hierarchy rule and the spreading policy. The controller node receives a reconfiguration of system deployment. The controller node distributes a second data object in the system based on providing protection of the protection level to the second data object without affecting protection of the same protection level applied to the first data object.