Abstract: A method and apparatus for synchronization between an originating node and an answering node. Given the fact that it is impossible to expect that independent time bases at the originate and answer node will oscillate at exactly the same frequency, the time base at the answer node is constrained to maintain an average frequency which is identical to that established by the originate node. The answer node monitors the status of a buffer in respect of almost-full and almost-empty conditions. A binary timing control signal is generated which switches to one state in response to an almost-fill condition and switches to an opposite state in response to an almost-empty condition. When the buffer is in an almost-full state, the operating clock at the answer node is controlled so as to be slightly higher than the frequency established by the originate node. In this way, a buffer which is in an almost-full state will tend to be emptied more rapidly (by the answer node's clock) than it is filled from the originate node.

Abstract: An improved correlator or matched filter for binary coefficients is provided which reduces the amount of logic required to indicate the receipt of a predetermined code word. The matched filter includes a plurality of stages of delay, where the number of stages in the delay is preferably equal to the product of the number of chips in the code word and the number of times each chip is sampled. Logic input locations are selected corresponding to transitions in the code word. Digital logic responds to signals available at each logic input for generating data indicating the change in the degree of match between the received signal samples and the code word. An integrator is the last element in the logic and is provided with the foregoing change information. The output of the integrator is then an indication of the degree of match between the most recent set of signal transitions corresponding to the number of transitions in the sampled code word and the code word itself.