Abstract: A device and a method for integrated circuit assistance design, and a method for constructing an electrical performance gradient model are provided. The device includes a database and a processor. The database has an electrical performance gradient model. The electrical performance gradient model represents a gradient distribution of an electrical performance in a wafer. The processor is coupled to the database. The processor analyzes a designed circuit by using the electrical performance gradient model.

Abstract: A device and a method for integrated circuit assistance design, and a method for constructing an electrical performance gradient model are provided. The device includes a database and a processor. The database has an electrical performance gradient model. The electrical performance gradient model represents a gradient distribution of an electrical performance in a wafer. The processor is coupled to the database. The processor analyzes a designed circuit by using the electrical performance gradient model.

Abstract: A setup time and hold time detection system including a monitoring unit and a processing unit. The monitoring unit is configured to detect multiple setup times and multiple hold times of multiple test circuits through a source clock signal. The processing unit is configured to record multiple setup times and multiple hold times as multiple detection data. The processing unit is further configured to select a first part of the detection data as multiple first detection data to establish an estimation model. The processing unit is further configured to select a second part of the detection data as multiple second detection data, and compare the second detection data and multiple estimation results generated by the estimation model to obtain an error value of the estimation model.

Abstract: A clock and data recovery circuit includes a first sampling phase detector and filter circuitry, a frequency detector circuit, a current source circuit, a band controller circuit, and a voltage controlled oscillator. The first sampling phase detector and filter circuitry generates a first voltage according to a pair of data and a first set of clock signals. The frequency detector circuit generates an up control signal and a down control signal according to the pair of data and the first set of clock signals. The current source circuit generates the first voltage according to the up control signal and the down control signal. The band controller circuit generates a band control signal according to the first voltage. The voltage controlled oscillator adjusts the first set of clock signals according to the band control signal and the first voltage.

Abstract: A memory device including a voltage boosting circuit, a switching circuit and a word line driving circuit is provided. The voltage boosting circuit is activated in a sleep mode. The voltage boosting circuit, based on an activation signal, performs a voltage boosting operation on a power voltage of a power voltage rail to generate a boosting voltage and transmit the boosting voltage to a control voltage rail. The switching circuit is turned on or cut-off according to a first mode selection signal. The word line driving circuit generates a plurality of word line signals according to the boosting voltage in the sleep mode; in addition, the word line driving circuit generates the word line signals according to the power voltage in a normal mode.

Abstract: A wafer characteristic prediction method and an electronic device are provided. The method includes: receiving a process parameter of a wafer during a mass production; inputting the process parameter to a prediction model to obtain a wafer characteristic of the wafer being mass produced; and outputting the wafer characteristic.

Abstract: A semiconductor apparatus includes a plurality of chips and a first bypass switch. The chips are coupled in series between a power end and a reference ground end. The first bypass switch is coupled in series between a first end and a second end of a first chip among the chips, wherein the first end is coupled to the power end and the second end is coupled to the reference ground end. The first bypass switch is turned on according to a first control signal when an operational efficiency of the first chip is less than a threshold value and the first chip is determined to be damaged.

Abstract: A dynamic flip flop is provided. The dynamic flip-flop comprises a transmission gate, a first inverter, a second inverter, a pull-up transistor and a pull-down transistor. The pull-up transistor and the pull-down transistor constitute a feedback inverter, and the feedback inverter is configured as a weak keeper circuit compared to the first inverter serving as a tri-state inverter. Therefore, the dynamic flip-flop can be such that makes a master latch to use the tri-state inverter for capturing data in order to reduce electric leakage. In addition, the dynamic flip-flop can also be such that makes a slave latch to use the weak keeper circuit for storing data, thereby avoiding floating point to drive the output.

Abstract: An embodiment of the invention provides a multi-bit flip-flop. The multi-bit flip-flop includes a clock input pin, a clock buffer circuit, and a plurality of flip-flops. The clock buffer circuit is used to receive a first clock signal received from the clock input pin and provide a second clock signal and a third clock signal according to the first clock signal. Each of the plurality of flip-flops is used to receive the second clock signal and the third clock signal and store data according to the second clock signal and the third clock signal. Therefore, the multi-bit flip-flop is designed such that makes each of the plurality of flip-flops to share the same clock.

Abstract: A compressor, an adder circuit, and an operation method thereof are provided. The compressor includes a first adder circuit and a second adder circuit. The first adder circuit receives a plurality of input values. The first adder circuit outputs a first inverted sum value (an inverted signal of a sum value) and a first inverted carry value (an inverted signal of a carry value). One of a plurality of input terminals of the second adder circuit is coupled to the first adder circuit to receive one of the first inverted sum value and the first inverted carry value. The second adder circuit outputs a second inverted sum value and a second inverted carry value.

Abstract: A wafer characteristic prediction method and an electronic device are provided. The method includes: receiving a process parameter of a wafer during a mass production; inputting the process parameter to a prediction model to obtain a wafer characteristic of the wafer being mass produced; and outputting the wafer characteristic.

Abstract: A semiconductor apparatus includes a plurality of chips and a first bypass switch. The chips are coupled in series between a power end and a reference ground end. The first bypass switch is coupled in series between a first end and a second end of a first chip among the chips, wherein the first end is coupled to the power end and the second end is coupled to the reference ground end. The first bypass switch is turned on according to a first control signal when an operational efficiency of the first chip is less than a threshold value and the first chip is determined to be damaged.

Abstract: A receiver circuit includes a first amplifier circuit, a second amplifier circuit, and a selector circuit. The first amplifier circuit is configured to receive a pair of receiving signals. The second amplifier circuit is configured to receive the pair of receiving signals. Based on a selection signal, the first amplifier circuit generates a pair of first amplifying signals according to the pair of receiving signals or the second amplifier circuit generates a pair of second amplifying signals according to the pair of receiving signals. The selector circuit is configured to output the pair of first amplifying signals or the pair of second amplifying signals according to the selection signal.

Abstract: An integrated circuitry includes a first circuit, a second circuit, and a voltage conversion circuit. A first power supply positive terminal of the first circuit is electrically coupled to a power source. The second circuit is electrically coupled in series with the first circuit and the power source. A second power supply positive terminal of the second circuit is electrically coupled to a first power supply negative terminal of the first circuit. The voltage conversion circuit is electrically coupled between the first circuit and the second circuit so as to receive a signal from the first circuit or the second circuit. The voltage conversion circuit converts a voltage value of the signal according to a first low potential signal of the first power supply negative terminal and a second low potential signal of a second power supply negative terminal.

Abstract: A data latch circuit and a pulse signal generator thereof are provided. The pulse signal generator includes a first buffer, a second buffer, a pull-up switch and an output buffer. The first buffer generates a first buffering signal according to an input signal and a feedback signal. The second buffer generates a second buffering signal according to the input signal and the first buffering signal. The pull-up switch pulls up the second buffering signal according to the first buffering signal. The output buffer generates at least one output pulse signal according to the second buffering signal. The output buffer further outputs the at least one output pulse signal to the first buffer to be the feedback signal.