Abstract: A Conductive Epoxy Coating (“CEC”) process is provided for assembling semiconductor devices. The CEC process includes application of a conductive epoxy coating prior to wafer dicing and instead of dispensing epoxy/solder when performing die bonding. The CEC process generally begins with a silicon wafer. Processing of the silicon wafer includes coupling a conductive epoxy layer to a first side of the semiconductor wafer to form a coated wafer. The process cures the coated wafer and forms die from the coated wafer. The process further couples an exposed side of the conductive epoxy layer of the die to a lead frame to form a semiconductor device, and cures the semiconductor device.

Abstract: In one embodiment the present invention includes a semiconductor rectifier device comprising a first, second, and third semiconductor regions and a gate. The first semiconductor region is of a first conductivity type. The second semiconductor region is adjacent to the first semiconductor region which has a second conductivity type. The third semiconductor region is adjacent to the second semiconductor region which has the second conductivity type. The gate is proximate to but insulated from the second semiconductor region and electrically coupled to the third semiconductor region. When the first semiconductor region is biased in a first direction, an inversion region forms in the second semiconductor region. The inversion region forms a forward-biased tunnel diode junction with the third semiconductor region. When the first semiconductor region is biased a second direction, the semiconductor rectifier device functions as a reverse-biased PIN diode.

Abstract: In one embodiment the present invention includes a semiconductor power device. The semiconductor power device includes a single gauge lead frame, a semiconductor die, and a heat sink. The semiconductor die is attached to a first level of the lead frame. The heat sink is attached to a second level of the lead frame. A molding compound encapsulates the semiconductor die and a portion of the lead frame, such that a portion of the heat sink is outside of the molding compound. The resulting device may be efficiently manufactured as compared to dual gauge lead frame devices or devices where the semiconductor die is not attached to the lead frame.

Abstract: In one embodiment the present invention includes a voltage converter operable in both buck and boost modes. The voltage converter may only include one switched capacitor. A programmable current source, which may be implemented as a switch array, generates a current into the switch capacitor during a first time period to produce a voltage across the capacitor. During a second time period, the voltage may be transferred to the output of the converter, or boosted by coupling the input voltage to one terminal of the switched capacitor coupling the other terminal of the capacitor to the output. A feedback circuit is coupled to a controller for reprogramming the current into the capacitor to maintain the output voltage at desired levels.

Abstract: A semiconductor device is provided having a single-piece clip that interlocks into a lead frame using one or more forks on the clip that mate with one or more corresponding slots in the lead frame. A semiconductor die is mounted to a pad of the lead frame and the clip couples the die to a conductive lead of the lead frame. The interlocking coupling forms a lever that allows adjustment of a position of the clip relative to a region of the semiconductor die. Interference between the clip fork and a slot corresponding to the clip fork confines the lever motion or pivoting of the clip relative to the mounted semiconductor die. The coupling between the clip fork and the slot furthermore confines motion of the clip in each of a first dimension and a second dimension relative to a position of the lead frame.

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.