Patents Assigned to Dionics, Inc.
  • Patent number: 4931656
    Abstract: A dynamic discharge circuit for a capacitively-charged electrical device includes, in one embodiment, a bipolar transistor placed in the discharge path, with the base of the transistor being connected so that conduction is held off by the voltage generated by an illuminated PV-diode. When the PV-diode is shut off, base-drive is immediately supplied through a base resistor in dynamic fashion by the very capacitive charge that is to be discharged. In another embodiment, the resistor is replaced with a diode-transistor combination, thus eliminating the delaying RC product inherent with the use of a resistor. In yet a further embodiment, an SCR placed in the discharge path is also dynamically driven. Discharge times on the order of about 5 microseconds are attained with the latter two embodiments and it is found that this discharge time is relatively constant regardless of the value of the capacitance to be discharged.
    Type: Grant
    Filed: March 7, 1988
    Date of Patent: June 5, 1990
    Assignee: Dionics Inc.
    Inventors: Kenneth Ehalt, William Sheng, Bernard L. Kravitz
  • Patent number: 4912335
    Abstract: A dynamic discharge circuit for a capacitively-charged electrical device includes, in one embodiment, a bipolar transistor placed in the discharge path, with the base of the transistor being connected so that conduction is held off by the voltage generated by an illuminated PV-diode. When the PV-diode is shut off, base-drive is immediately supplied through a base resistor in dynamic fashion by the very capacitive charge that is to be discharged. In another embodiment, the resistor is replaced with a diode-transistor combination, thus eliminating the delaying RC product inherent with the use of a resistor. In yet a further embodiment, an SCR placed in the discharge path is also dynamically driven. Discharge times on the order of about 5 microseconds are attained with the latter two embodiments and it is found that this discharge time is relatively constant regardless of the value of the capacitance to be discharged.
    Type: Grant
    Filed: February 28, 1989
    Date of Patent: March 27, 1990
    Assignee: Dionics Inc.
    Inventors: Kenneth Ehalt, William Sheng, Ronald P. Colino, Bernard L. Kravitz
  • Patent number: 4074293
    Abstract: A PN junction having very low concentration gradients on both sides exhibits substantially increased breakdown voltages. A PN junction extending to the surface of a semiconductive body is formed by diffusing material of a first conductivity type into material of a second conductivity type in two stages: in the first stage, the surface concentration of impurity atoms is no higher than about 10.sup.16 per cc., and is always two to four orders of magnitude less than conventional junctions. In the second stage, the area of diffusion is smaller, so as to be surrounded by the area of said first stage diffusion, but concentration and depth are at normal levels, roughly 10.sup.17 - 10.sup.20. The higher the concentration is in the second stage, the greater the concentration difference between the two stages must be. Breakdown voltages of devices employing the junction of the invention are improved: planar transistors with BV.sub.cbo = 1000 volts may be produced.
    Type: Grant
    Filed: November 15, 1973
    Date of Patent: February 14, 1978
    Assignee: Dionics, Inc.
    Inventor: Bernard L. Kravitz
  • Patent number: 4068255
    Abstract: The voltage characteristics of switching integrated circuits of the type disclosed in U.S. Patent No. 3,918,083 are improved by employing a mesa-type etch to physically separate the four vertical transistors. Interconnection may be carried out by wire bonding respective collector and emitter areas or, preferably, passivating materials are used to fill the etched grooves and interconnection is carried out by vapor deposition (e.g. planar) techniques.
    Type: Grant
    Filed: December 23, 1976
    Date of Patent: January 10, 1978
    Assignee: Dionics, Inc.
    Inventors: Bernard L. Kravitz, George R. Seaton
  • Patent number: 4001866
    Abstract: A photosensitive integrated circuit switch that operates in the same manner as back-to-back photosensitive SCR's. The invention combines the monolithic, junction-isolated construction of the basic photrac, described in U.S. Pat. No. 3,918,083, and the operational characteristics of a dielectrically isolated photrac, described in co-pending application Ser. No. 616,040, but incorporates the single-quadrant gate-triggering feature of the latter. Its simplified construction makes it advantageous in many applications.
    Type: Grant
    Filed: October 16, 1975
    Date of Patent: January 4, 1977
    Assignee: Dionics, Inc.
    Inventors: Bernard L. Kravitz, George R. Seaton
  • Patent number: 4001867
    Abstract: A bilateral, switching integrated circuit is described in U.S. Pat. No. 3,918,083. The present application discloses variations of the basic structure and devices incorporating both the basic structure and the variants. Included are a photosensitive, zero-crossing optoisolator, relay structures, a switch of greatly increased light sensitivity employing photodarlingtons, and a dielectrically isolated switch that can be triggered by light or gated injection currents.
    Type: Grant
    Filed: September 23, 1975
    Date of Patent: January 4, 1977
    Assignee: Dionics, Inc.
    Inventors: Bernard L. Kravitz, George R. Seaton