Abstract: To satisfactorily apply a protective tape to a bump wafer, an application apparatus (1) for applying a protective tape (PT) to a wafer (W) includes: an application table (60) configured to support the wafer (W); a tape holding body (30) capable of holding the protective tape (PT) and configured to supply the protective tape (PT) held by the tape holding body (30) onto the wafer (W); and a pressing member (62) configured to press the protective tape (PT) from above. The pressing member (62) includes a protective layer outer periphery retainer (620) configured to press a peripheral portion of a protective layer (PL), which is laminated on the protective tape (PT) and has an outer diameter smaller than an outer diameter of the wafer (W), to apply the protective tape (PT) to the wafer (W).

Abstract: To reduce residual stress generated on a protective tape at a time of application of the protective tape to a semiconductor wafer, provided is an application apparatus (1) for applying a protective tape (PT) to a semiconductor wafer (W), including: a tape conveyance mechanism (2) configured to convey the protective tape (PT) temporarily applied to a base material (BM) to a peeling position; a tape holding body (30) capable of holding the protective tape (PT); a holding-body moving mechanism (31) configured to move the tape holding body (30) to the peeling position; and a peeling mechanism (4) configured to peel the base material (BM) from the protective tape (PT) held by the tape holding body (30) at the peeling position.

Abstract: To satisfactorily apply a protective tape to a bump wafer, an application apparatus (1) for applying a protective tape (PT) to a wafer (W) includes: an application table (60) configured to support the wafer (W); a tape holding body (30) capable of holding the protective tape (PT) and configured to supply the protective tape (PT) held by the tape holding body (30) onto the wafer (W); and a pressing member (62) configured to press the protective tape (PT) from above. The pressing member (62) includes a protective layer outer periphery retainer (620) configured to press a peripheral portion of a protective layer (PL), which is laminated on the protective tape (PT) and has an outer diameter smaller than an outer diameter of the wafer (W), to apply the protective tape (PT) to the wafer (W).

Abstract: Disclosed is a method for generating chip stacks during the production of chips from wafers, the chips located on the wafer being separated from one another, the wafer being ground thin and the chips being stacked to form chip stacks, the chips being checked for the purpose of a functional check, characterized in that the chips are checked in a first work step, that adhesive material is applied on the good chips, whereas the bad chips are not provided with adhesive material, that the wafer is assembled and ground thin afterwards and that the bad chips are subsequently removed and replaced by good chips.