Abstract: Systems and methods for facilitating compliance with FCC frequency hopping requirements are described. The described innovations may be used to facilitate frequency hopping in a sensor network having a network link with two endpoints, those endpoints comprising a master and a slave, wherein the slave comprises a server and the master comprises a sensor, and wherein the slave transmits one message in response to each master message on the link. All communication over the link may be initiated by the master terminal, requiring only one return message per transmission. A channel to be used for a following reception from the slave terminal is specified at the master, and the specified channel is transmitted from the master to the slave terminal. The slave terminal then uses the specified channel for its next transmission.

Abstract: A method for pairing a first network device with a second network device is provided. The method may include receiving a first signal corresponding to a first pairing sequence received at the first network device, receiving a second signal corresponding to a second pairing sequence received at the second network device, comparing the first pairing sequence with the second pairing sequence, and pairing the first network device and the second network device when the second pairing sequence correlates to the first pairing sequence.

Abstract: A relaxation oscillator circuit includes a current mirror configured to receive the input current from the and generate a plurality of starved currents, a Schmitt trigger configured to be current starved by a first starved current of the plurality of starved currents and a plurality of inverters configured to receive a Schmitt trigger output signal and generate an output clock signal, the inverters including a plurality of current starved inverters that are current starved by a second starved current of the plurality of starved currents, the plurality of current starved inverters receiving the Schmitt trigger output signal and generating a first inverter output signal, upon which an output clock signal is based. The relaxation includes a capacitor configured to charge or discharge in response to the output clock signal and a switching module configured to provide current from the current source based on the output clock signal.

Abstract: An ADC method and system implement a comparison stage of SAR ADC directly in the analog domain rather than the digital domain, without resolving the output word Dout. This means that the number of comparisons, and thus the numbers of required periods of CK, equals number of threshold values instead of equaling the number of bits in the resolved output word. In this way, power is saved in the analog domain as well as in the digital domain.

Abstract: A bias circuit is provided. The bias circuit may include a first transistor forming an input node, a second transistor forming an output node, and a switch array disposed between the first transistor and the second transistor. The switch array may be configured to charge the first transistor to a supply voltage and the second transistor to a ground during a first mode of operation, and couple the first transistor to the second transistor to approximate a final bias voltage during a second mode of operation.

Abstract: A method of testing a self-contained device under test having at least a circuit under test and a power source is provided. The method may include at least temporarily enabling power from the power source to the circuit under test, determining a first voltage across the circuit under test, determining a second voltage across the circuit under test after a test duration, and calculating an average current of the circuit under test based at least partially on the first voltage, the second voltage and the test duration.

Abstract: A method of establishing an asymmetric network between at least one node device and a gateway device is provided. The method may include transmitting a reduced data package from the node device, receiving the reduced data package in a data stream at the gateway device, validating bits of the data stream, and retrieving the reduced data package based on the validated bits.

Abstract: A method for pairing a first network device with a second network device is provided. The method may include receiving a first signal corresponding to a first pairing sequence received at the first network device, receiving a second signal corresponding to a second pairing sequence received at the second network device, comparing the first pairing sequence with the second pairing sequence, and pairing the first network device and the second network device when the second pairing sequence correlates to the first pairing sequence.

Abstract: A relaxation oscillator circuit includes a current mirror configured to receive the input current from the and generate a plurality of starved currents, a Schmitt trigger configured to be current starved by a first starved current of the plurality of starved currents and a plurality of inverters configured to receive a Schmitt trigger output signal and generate an output clock signal, the inverters including a plurality of current starved inverters that are current starved by a second starved current of the plurality of starved currents, the plurality of current starved inverters receiving the Schmitt trigger output signal and generating a first inverter output signal, upon which an output clock signal is based. The relaxation includes a capacitor configured to charge or discharge in response to the output clock signal and a switching module configured to provide current from the current source based on the output clock signal.

Abstract: An ADC method and system implement a comparison stage of SAR ADC directly in the analog domain rather than the digital domain, without resolving the output word Dout. This means that the number of comparisons, and thus the numbers of required periods of CK, equals number of threshold values instead of equaling the number of bits in the resolved output word. In this way, power is saved in the analog domain as well as in the digital domain.

Abstract: A method of performing out-of-band commissioning is provided. The method may include enabling a pairing mode on a commissioning device, generating a gesture code on the commissioning device, receiving a gesture input on a node device, verifying an agreement between the gesture code and the gesture input, and commissioning the node device based on the agreement.

Abstract: A source follower for a capacitive sensor device having a sense node and a shield node is provided. The source follower may include a transistor, and a switch array selectively coupling the transistor between the sense node and the shield node. The switch array may be configured to substantially disable current to the transistor during a first mode of operation, precharge the transistor during a second mode of operation, and enable the transistor to copy a sense node voltage to a shield node voltage during a third mode of operation.

Abstract: A capacitive sensor device is provided. The capacitive sensor device may include a clock module configured to generate a clock signal, a sensor module configured to generate a reference signal and a sense signal, and sample a difference between the reference signal and the sense signal according to the clock signal, and a current supply module configured to selectively generate a bias current according to the clock signal, and charge each of the clock module and the sensor module based on the bias current and according to the clock signal.

Abstract: A method of actively draining a power supply of a device circuit is provided. The method may include monitoring an output voltage of the power supply relative to a first lower limit, enabling an active drain circuit to actively drain the power supply when the output voltage falls below the first lower limit, monitoring the output voltage of the power supply relative to a second lower limit that is less than the first lower limit, and disabling the active drain circuit when the output voltage falls below the second lower limit.

Abstract: A self-clocked SAR ADC sensor circuit includes an ADC having a capacitor array with a plurality of capacitors connected through a respective plurality of switches, a comparator, an SAR module, and a delay element circuit for ring oscillator and stall detection. The delay element circuit includes a delay block with a NAND gate followed by a plurality of inverters.

Abstract: A clock delay circuit is configured to generate a delayed clock signal based on an input clock signal, the delayed clock signal delayed by a delay time (TDEL). The circuit includes a current mirror configured to generate starved currents based on the reference current, a plurality of inverters, and a Schmitt trigger configured to generate an output signal in response to the input clock signal, wherein the Schmitt trigger output signal increases from a low signal to a high signal over a period (TCHARGE) correlated with TDEL. Some inverters and the Schmitt trigger are configured to be current starved when the input clock signal is high and are configured to be shorted to ground and the reference current when the input clock signal is low. TDEL is based on TCHARGE and TCHARGE is based on C, NTOP, VST,High, and a supply voltage.

Abstract: A method of tuning antenna match is provided. The method may include providing a matching network of inductors and capacitors configured to match an impedance of an antenna, monitoring a voltage of the matching network, and adjusting an effective value of one or more of the inductors and the capacitors of the matching network when the voltage indicates a decrease in match quality. A radio frequency (RF) device is also provided. The RF device may include a ground layer defining a perimeter thereabout and having a ground pattern therein, a device circuit disposed on the ground pattern and within the perimeter, and an antenna coupled to the device circuit and disposed at least partially along the perimeter about the ground layer.