Abstract: The present invention is to provide a computer for backup and being fault-tolerant comprising a CPU connected to an I/O port, a dual-port memory, a memory address decoder, a bus tri-state buffer, and an arbitration circuit, where the CPU can access data of the dual-port memory based on a decoded memory address of the memory address decoder, first and second ports of the dual-port memory are connected to input and output of the bus tri-state buffer respectively, and an output of the arbitration circuit is connected to an enable terminal of the bus tri-state buffer.

Abstract: The present invention discloses a processor capable of alerting its life expectancy and its method. The processor is installed in an electronic device having a control circuit, a frequency divider circuit and a time counter. The control circuit is connected to the frequency divider circuit and the time counter. The frequency divider circuit receives a plurality of high frequencies from the control circuit and converts the high frequencies into a time unit. The time counter adds the time units one by one to obtain a use time. If the use time has reached a predetermined use time, the control circuit will issue a warning to indicate that the life expectancy of the processor is reached, so as to reflect the actual use time of the processor, prevent a change of use time by software, and allow users to timely take proper preventive measures before the processor exceeds its life cycle.

Abstract: The present invention is to provide a computer for backup and being fault-tolerant comprising a CPU connected to an I/O port, a dual-port memory, a memory address decoder, a bus tri-state buffer, and an arbitration circuit, where the CPU can access data of the dual-port memory based on a decoded memory address of the memory address decoder, first and second ports of the dual-port memory are connected to input and output of the bus tri-state buffer respectively, and an output of the arbitration circuit is connected to an enable terminal of the bus tri-state buffer.

Abstract: The present invention discloses a processor capable of alerting its life expectancy and its method. The processor is installed in an electronic device having a control circuit, a frequency divider circuit and a time counter. The control circuit is connected to the frequency divider circuit and the time counter. The frequency divider circuit receives a plurality of high frequencies from the control circuit and converts the high frequencies into a time unit. The time counter adds the time units one by one to obtain a use time. If the use time has reached a predetermined use time, the control circuit will issue a warning to indicate that the life expectancy of the processor is reached, so as to reflect the actual use time of the processor, prevent a change of use time by software, and allow users to timely take proper preventive measures before the processor exceeds its life cycle.