Patents Assigned to Doides Incorporated
  • Patent number: 9893512
    Abstract: Damages to the rectifying MOSFET in the secondary side of voltage converters are reduced or eliminated by inserting intermediary steps between detecting a dropping in the converter output voltage VCC and activating the under voltage lock out (UVLO) circuitry. During the intermediary steps, the timing for switching off the MOSFET is advanced to prevent the current flow in the MOSFET from reversing its direction.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: February 13, 2018
    Assignee: Doides Incorporated
    Inventors: Frederick Leung, Ang Yong