Abstract: The present disclosure relates to an adaptive body biasing or voltage regulation circuit for a circuit region, comprising: a first delay module configured to delay a local clock signal to generate first and second output signals delayed by first and second delays; a multiplexer configured to select one of the first and second output signals; a first slack monitor circuit configured to generate a first detection signal indicating when a slack time of the first and second output signals is less than a first threshold; a voltage generation circuit configured to generate a supply voltage for the circuit region, or at least one biasing voltage for biasing wells of transistors in the circuit region, using a further control loop comprising a process, voltage and/or temperature sensor; and a control circuit configured to adjust a gain of the further control loop based on the first detection signal.

Abstract: A D-type flip-flop circuit 1 has a structure in which a pMOS transistor p8 and an nMOS transistor n8 are added to a general D-type flip-flop circuit comprising pMOS transistors p1 to p7, p11 to p15 and nMOS transistors n1 to n7, n11 to n15.

Abstract: The invention concerns a computing system comprising: an island (102) comprising a group of circuits capable of operating in one of a plurality of operating modes, the island being coupled to an island control circuit (122); and a clock generation circuit (902) supplying a further clock signal to the island control circuit (122) for controlling a change of mode of the island, the clock generation circuit (902) being configured to select one of a plurality of clock frequencies for the further clock signal, the selection being based on the change of operating mode to be applied.

Abstract: Embodiments of the present technology provide a synchronous device. The synchronous device provides a first latch configured to store a data input signal during a first state of a first clock signal and a slack guard circuit. The slack guard circuit provides a delay element coupled to the first latch and configured to generate a delayed data signal, a gated-input cell coupled to the delay element and configured to propagate the delayed data signal during the first state of the first clock signal, and a comparator coupled to the first latch and the gated-input cell.