Abstract: A method for coupling a differential signal generated by a digital processing unit includes high-pass filtering the differential signal. The filtered output of the high-pass filter is then provided to an input of a differential amplifier, the output of which is fed back to the input of the differential amplifier.

Abstract: A method for coupling a differential signal generated by a digital processing unit includes high-pass filtering the differential signal. The filtered output of the high-pass filter is then provided to an input of a differential amplifier, the output of which is fed back to the input of the differential amplifier.

Abstract: A general purpose computer system is equipped with apparatus for enabling a processor to provide efficient execution of multiple instructions per clock cycle. The major feature is a decoded instruction cache with multiple instructions per cache line. During run time cache hits, the decode logic fills the cache line with instructions up to its limit. During run time cache misses, the cache line enables the processor to dispatch multiple instructions during one clock cycle. Hereby is achieved high performance with a simple, but still powerful, decode and dispatch logic.An important feature of the instruction cache is that it holds the target addresses for the next instructions. No separate address logic is needed to proceed in the program execution during cache hits. A conditional branch holds its alternative target address in a separate field. This enables the processor, to a large degree, to be independent of the conditional branch bottleneck.