Abstract: The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.

Abstract: A method for coupling a differential signal generated by a digital processing unit includes high-pass filtering the differential signal. The filtered output of the high-pass filter is then provided to an input of a differential amplifier, the output of which is fed back to the input of the differential amplifier.

Abstract: A method for coupling a differential signal generated by a digital processing unit includes high-pass filtering the differential signal. The filtered output of the high-pass filter is then provided to an input of a differential amplifier, the output of which is fed back to the input of the differential amplifier.

Abstract: A scalable coherent interface (SCI) architecture delivers a high speed unidirectional signal from one SCI node to a next successive SCI node. The signal includes a data portion, e.g., SCI symbol, and a clock portion, e.g., a symbol separator. The clock portion indicates when the data portion may be sampled when collecting a sequence of SCI symbols. Relative timing between bits of the data portion and between the data portion as a whole and the symbol separator clock becomes skewed during transmission. The receiving node introduces delay in the clock portion as a function of detected stability in a synchronizing packet. A plurality of data registers are cyclicly written in response to the delayed clock portion whereby a single one of said registers at a given time is concurrently clocked and enabled. A control device monitors enable signals applied to the registers and in coordinated fashion cyclically reads SCI symbols therefrom.

Abstract: A general purpose computer system is equipped with apparatus for enabling a processor to provide efficient execution of multiple instructions per clock cycle. The major feature is a decoded instruction cache with multiple instructions per cache line. During run time cache hits, the decode logic fills the cache line with instructions up to its limit. During run time cache misses, the cache line enables the processor to dispatch multiple instructions during one clock cycle. Hereby is achieved high performance with a simple, but still powerful, decode and dispatch logic.An important feature of the instruction cache is that it holds the target addresses for the next instructions. No separate address logic is needed to proceed in the program execution during cache hits. A conditional branch holds its alternative target address in a separate field. This enables the processor, to a large degree, to be independent of the conditional branch bottleneck.