Abstract: A scalable coherent interface (SCI) architecture delivers a high speed unidirectional signal from one SCI node to a next successive SCI node. The signal includes a data portion, e.g., SCI symbol, and a clock portion, e.g., a symbol separator. The clock portion indicates when the data portion may be sampled when collecting a sequence of SCI symbols. Relative timing between bits of the data portion and between the data portion as a whole and the symbol separator clock becomes skewed during transmission. The receiving node introduces delay in the clock portion as a function of detected stability in a synchronizing packet. A plurality of data registers are cyclicly written in response to the delayed clock portion whereby a single one of said registers at a given time is concurrently clocked and enabled. A control device monitors enable signals applied to the registers and in coordinated fashion cyclically reads SCI symbols therefrom.