Abstract: The present disclosure relates to a clock generator comprising: a ring oscillator configured to generate an output frequency signal; a frequency detector configured to compare a frequency of the output frequency signal with r times a frequency of a reference frequency signal and to generate a feedback signal; and a control circuit configured to: control a loop delay parameter of the ring oscillator and a supply voltage of the ring oscillator based on the feedback signal; reduce the frequency of the output frequency signal when its frequency is higher than r times the frequency of the reference frequency signal by reducing the supply voltage; and increase the frequency of the output frequency signal when its frequency is lower than r times the frequency of the reference frequency signal by reducing the loop delay parameter.

Abstract: The present disclosure relates to a circuit comprising: —a first timing guard circuit (200) configured to detect when a slack time of a first data signal arriving at a first synchronous device (202) falls below a first threshold (SLG DELAY); and —a second timing guard circuit (200) configured to detect when a slack time of a second data signal arriving at a second synchronous device (202) falls below a second threshold (SLG DELAY), the first and second thresholds being different from each other.