Abstract: In a method of manufacturing a CMOS transistor, an n-channel MOS transistor is formed on an upper MOS transistor in a first region of an SOI substrate having first and second regions. Next, an insulating layer of the SOI substrate is exposed by removing an upper silicon layer in a second region, and then, a first insulating layer is formed to cover the first and second regions. Next, a silicon epitaxial layer is formed on the first insulating layer of the second region, and then, a p-channel MOS transistor is formed on the silicon epitaxial layer. An n-channel MOS transistor is formed on the upper silicon layer of the SOI substrate and a p-channel MOS transistor on the first insulating layer has a vertical step (relative to the n-channel MOS transistor), so that it is possible to increase integration degree.