Abstract: A method of measuring a shifted extent of a shifted epitaxy layer by an N+ buried layer using difference between contact resistances is described. An N-type buried layer comprising a stepped portion is formed at a P-type substrate. An epitaxy layer is formed, comprising a stepped portion, on the N-type buried layer. A plug is formed in the epitaxy layer. An insulating layer is formed on the epitaxy layer. A plurality of contacts are formed in the insulating layer. Resistances of the plurality of contacts are measured and a shifting extent of the stepped portion of the epitaxy layer is calculated using the plurality of contact resistances.

Abstract: A method is provided in which a first oxide layer is deposited on a silicon substrate and etched to form openings. A first silicon epitaxial layer is grown on the substrate in the openings, forming first active regions, a second oxide layer is deposited thereon, and the first and second oxide layers are etched such that the first oxide layer is wholly removed and the second oxide layer remains only on the first silicon epitaxial layer. A third oxide layer is thermally grown on entire resultant surfaces and then blanket-etched to remain only on sidewalls of the first silicon epitaxial layer. A second silicon epitaxial layer is grown on the exposed substrate between the first active regions, thus forming second active regions. The second oxide layer remaining on the first silicon epitaxial layer is removed. The first and second active regions are separated and electrically isolated by the third oxide layer.

Abstract: A method for forming a dual damascene interconnection in a semiconductor device. An etch stop film and an intermetal insulating film are formed sequentially on a lower metal film. A via hole is formed to expose a portion of a surface of the etch stop film through the intermetal insulating film. A sacrificial film is formed to fill the via hole. Portions of the intermetal insulating film and the sacrificial film are removed to form a trench. The sacrificial film is removed to expose the portion of the surface of the etch stop film. A plasma etching process is performed at a predetermined temperature using an etching gas to remove the exposed portion of the etch stop film and to prevent or suppress generation of a polymer. A diffusion barrier film is formed within the trench and the via hole such that the diffusion barrier contacts the lower metal film. An upper metal film is formed on the diffusion barrier.

Abstract: A method for fabricating a split gate flash memory includes depositing a second conductive layer for forming a control gate on a semiconductor substrate having a first conductive layer, an insulating layer, and an oxide layer on both sides of the first conductive layer formed thereon, filling an anti-implant protective layer in a depression of the second conductive layer, performing ion implant on the second conductive layer, removing the anti-implant protective layer filled in the depression of the second conductive layer, forming a photoresist pattern by depositing a photoresist layer on the second conductive layer for forming a control gate, and treating the photoresist layer with a light exposure and a development process, and forming the control gate by etching the second conductive layer.

Abstract: Method for forming contact electrodes in a semiconductor device are disclosed. An example method comprises sequentially forming a pad oxide layer, a pad nitrate layer, a dummy oxide layer, and a capping nitride layer on a substrate. These layers and the substrate are then patterned to form a trench. The trench us filled with an insulating material to form a device isolation stripe. The resulting structure is then patterned to form a trench. Spacers are formed on the sidewalls of the trench and ions are implanted into the substrate beneath the trench to form local channel portions. A gate insulating layer and a gate electrode are then formed by deposition. Thereafter, the dummy oxide layer and the capping nitride layer are removed and source/drain portions are defined. Contact electrodes are then formed by deposition of a metal layer.